Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2008-04-22
2008-04-22
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Read/write circuit
Signals
C365S233100
Reexamination Certificate
active
11165797
ABSTRACT:
Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
REFERENCES:
patent: 5233557 (1993-08-01), Sakagami et al.
patent: 5579267 (1996-11-01), Koshikawa
patent: 5661688 (1997-08-01), Yim et al.
patent: 5835443 (1998-11-01), Fujita
patent: 5848260 (1998-12-01), Chen et al.
patent: 5886948 (1999-03-01), Ryan
patent: 5923615 (1999-07-01), Leach et al.
patent: 6016282 (2000-01-01), Keeth
patent: 6075730 (2000-06-01), Barth et al.
patent: 6101136 (2000-08-01), Mochida
patent: 6101138 (2000-08-01), Shiah et al.
patent: 6154821 (2000-11-01), Barth et al.
patent: 6266285 (2001-07-01), Farmwald et al.
patent: 6298004 (2001-10-01), Kawasaki et al.
patent: 6314051 (2001-11-01), Farmwald et al.
patent: 6327196 (2001-12-01), Mullarkey
patent: 6351433 (2002-02-01), Kosugi
patent: 6401167 (2002-06-01), Barth et al.
patent: 6449727 (2002-09-01), Toda
patent: 6539454 (2003-03-01), Mes
patent: 6640292 (2003-10-01), Barth et al.
patent: 6643787 (2003-11-01), Zerbe et al.
patent: 6788594 (2004-09-01), Ware et al.
patent: 6842864 (2005-01-01), Barth et al.
patent: WO 99/50852 (1999-10-01), None
400 Mb/s/pin SLDRAM Draft/Advance, 4M x 18 SLDRAM, Pipelined, Eight Bank, 2.5V Operation, Rev. Jul. 9, 1998, pp. 1-69, Calif., Copyright 1998, SLDRAM Inc.
Gillingham, Peter et al, “SLDRAM: High Performance Open-Standard Memory,” IEEE Micro, Nov./Dec. 1997, pp. 29-39, vol. 17, No. 6, Institute of Electrical and Electronics Engineers, Inc., Los Alamitos, California.
Gillingham, Peter, “SLDRAM Architectural and Functional Overview,” SLDRAM Consortium, SLDRAM Inc., pp. 1-14 Ontario, Canada(Aug. 29, 1997).
Micropresser and Microcomputer Standards Subcommittee of the IEEE Computer Society,“Draft Standard for a High-Speed Memory Interface (SyncLink),” Draft 0.99 IEEE P1596.7-199X, pp. 1-66, New York (1996).
Nakase, Yasunobu, et al., “Source-Synchronization and Timing Vernier Techniques for 1.2-GB/s SLDRAM Interface,” IEEE Journal of Solid-State Circuits, vol. 34, No. 4, pp. 494-501. Apr. 1999.
Paris Lluis et al., “WP 24.3: A 800 Mb/s 72 MB SLDRAM with Digitally-Calibrated DLL”, ISSCC, 0-7803-5129-0/99, 10 pages. Slide Supplement, IEEE, 1999.
Hampel Craig E.
Stark Donald C.
Tsern Ely K.
Ware Frederick A.
Hoang Huan
Rambus Inc.
Shemwell Mahamedi LLP
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