Asynchronous FIFO memory having built-in self test logic

Details Asynchronous FIFO memory having built-in self test logic Asynchronous FIFO memory having built-in self test logic

2002-10-22

2003-08-26

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Serial read/write

C365S189120, C365S220000

Reexamination Certificate

active

06611469

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to memory, and, more particularly, to a first-in/first-out memory having a built-in self test for an asynchronous memory.
BACKGROUND OF THE INVENTION
Asynchronous First-in, First-out (FIFO) memory devices allow data to be written to and read from a memory array at independent data rates. Reading or writing of data is done independently using separate asynchronous data blocks. Testing of the memory device after silicon fabrication ensures that all bits in the memory array function properly under any condition in which each device will, in all probability, be exposed to when inserted into any system. A memory-based FIFO utilizes a Random Access Memory (RAM) as its storage element. This RAM may have a single (combined) read/write port or separate (dual) ports for reading and writing data. The RAM further includes n storage rows or words, where n is an integer. Conventionally, for data storage in a computer system, FIFO memory devices typically include dual-port static RAMs. Simultaneous writing to and reading from these RAMs is required with few restrictions on signal timing. Any undesirable interaction between these writes and reads may lead to a write or read failure.
Conventional integrated circuit (IC) test equipment is able to perform extensive memory testing for a majority of possible failure mechanisms. This asynchronous testing is performed using separate and external testing equipment. This system uses programmable logic to generate input data patterns responsive to a write clock signal and expected output patterns responsive to a read clock signal. Other logic within the system compares the expected output data to the actual output data and indicates any mismatches between the two as well as information on the nature of the mismatch. With increasing data rates in FIFO memories, however, such a system is costly, time consuming, and difficult to implement. In addition, this equipment is generally not able to fully emulate an asynchronous system, especially at maximum specified operating frequencies.
From a reliability standpoint, it is desirable to test all aspects of the FIFO memory device. Yet, FIFO memory devices are conventionally tested using parametric, functional and asynchronous tests. Such tests, however, do not reliably detect all possible faults, including faults associated with the memory, the addressing mechanism, nor the overall functionality of the FIFO memory device. Thus, while fault models and tests for detecting faults in RAMs are known, presently no fault models and tests exist for fully testing dual-port asynchronous FIFO memory devices.
Therefore, a need exists for a FIFO memory including Built-In Self Test (BIST) logic having minimal external test equipment required to implement full frequency asynchronous testing.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of testing of asynchronous FIFO memory, the present invention teaches an asynchronous FIFO memory having built-in self test logic. The FIFO memory in accordance with the present invention includes a RAM connected to read and write address registers whereby a status flag generator connects to the read and write address registers to provide ready input and ready output signal. When the FIFO memory is not full, the ready input signal indicates that the FIFO memory is ready to accept a data write. The ready output signal indicates that valid data is on the output data bus. Further, the FIFO memory device includes a write and read data generator connected to the input data bus to receive a portion of the word to define a pattern sequence select used to generate write and expected read data patterns corresponding to each of the words in memory. A multiplexer connects the write data generator and the input data bus to the RAM; whereby, in response to a test mode signal, the multiplexer switches to provide words from the input data bus to the RAM in a normal mode of operation and to provide words form the write data generator to the RAM in a testing mode of operation. A read data error register receives data patterns generated from the read data generator and the output data bus to compare each bit on the output data bus with each bit of the expected read data pattern and, thereby, generate error signals regarding data mismatches as well as the nature of the mismatch to any external device which monitors the FIFO device during the testing mode of operation.
Advantages of this design include but are not limited to a inexpensive FIFO memory device having Built-In Self Test (BIST) logic that uses minimal external test equipment required to implement full frequency asynchronous testing of the memory device.


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