Asynchronous FIFO apparatus and method for passing data...

Details Asynchronous FIFO apparatus and method for passing data... Asynchronous FIFO apparatus and method for passing data...

2008-01-01

2008-01-01

Bocure, Tesfaldet (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

Reexamination Certificate

active

10812310

ABSTRACT:
An asynchronous FIFO apparatus includes a main FIFO memory, operable to store the data to be passed between the first and second clock domains, accessible from each clock domain under the control of an access pointer associated with that clock domain. For one or both of the clock domains, the amount of data accessible per clock cycle is variable. An auxiliary FIFO memory is associated with each clock domain in which the amount of data accessible per clock cycle is variable, and operable to store the access pointer used to access the main FIFO memory from its associated clock domain, and the access pointer being stored at a location of the auxiliary FIFO memory specified by an auxiliary access pointer. Routing logic passes the auxiliary access pointer to the other clock domain to enable that other clock domain to retrieve the access pointer stored in the auxiliary FIFO memory.

REFERENCES:
patent: 5619713 (1997-04-01), Baum et al.
Chau et al., “A 6.4 GBPS FIFO Design for 8-32 Two-Way Data Exchange Bus,” IEEE, 2002, pp. 772-775.

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