Asynchronous, dual-port, RAM-based FIFO with bi-directional addr

Details Asynchronous, dual-port, RAM-based FIFO with bi-directional addr Asynchronous, dual-port, RAM-based FIFO with bi-directional addr

1997-01-30

1999-09-21

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

711131, 36523005, G11C 700

Patent

active

059567481

ABSTRACT:
A memory system having a dual port first in, first out (FIFO) memory which performs read operations in synchronism with a read clock signal and write operations in synchronism with a write clock signal. The read clock signal is asynchronous with respect to the write clock signal. A synchronizing engine is provided to synchronize a current write address with the read clock signal, thereby creating a synchronized write address. The synchronizing engine further synchronizes a current read address with the write clock signal, thereby creating a synchronized read address. The synchronized write address is compared to the current read address to determine if a FIFO empty condition exists. Similarly, the synchronized read address is compared to the current write address to determine if a FIFO full condition exists.

REFERENCES:
patent: 4873703 (1989-10-01), Crandall et al.
patent: 4888741 (1989-12-01), Malinowski
patent: 5345419 (1994-09-01), Fenstermaker et al.
patent: 5365485 (1994-11-01), Ward et al.
patent: 5408673 (1995-04-01), Childers et al.
patent: 5555524 (1996-09-01), Castellano
patent: 5640528 (1997-06-01), Harney et al.

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