Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2002-06-04
2004-09-07
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C327S144000
Reexamination Certificate
active
06788109
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and particularly to a semiconductor integrated circuit that operates in sync with clock signals.
The conventional semiconductor integrated circuit of that type generally includes plural logic circuits, plural flip-flops each for synchronizing the logic circuits with clock signals, and a clock generation circuit, which are formed on a semiconductor chip. The clock generation circuit produces clock signals to flip-flops formed at various portions on the semiconductor chip, thus operating the whole circuit in a synchronous mode.
In order to improve the operational rate of the semiconductor integrated circuit, it is required to operate it at higher clock frequency. However, the conventional semiconductor integrated circuit has the disadvantage in that because the whole circuit operates in sync with a single clock signal, the clock skew caused by an increased logic scale and chip size makes it difficult to increase the clock frequency. The clock skew means a delay difference between time periods for which clock signals reach to flip-flops respectively. The skew tends to become larger as the logic scale and chip area of a semiconductor integrated circuit increase. Recently, semiconductor integrated circuits are increasing their logical scale and their chip area. This makes it more difficult to increase the operational speed of semiconductor integrated circuits.
SUMMARY OF THE INVENTION
The present invention is made to solve the above-mentioned problems. An object of the present invention is to provide a semiconductor integrated circuit capable of reducing the clock skew without being influenced by its logic scale and its chip area, thus improving its operational rate.
In order to accomplish the above-mentioned object, a semiconductor integrated circuit according to the present invention comprises a plurality of logic blocks formed on a semiconductor chip, the plurality of logic blocks being respectively operated in sync with clock signals unique to the plurality of logic blocks, data transfer between the plurality of logic blocks being performed in asynchronous transfer scheme.
According to the present invention, the semiconductor integrated circuit further comprises a data line for connecting a first logic block at a data transfer source and a second logic block at a data transfer destination; and a clock line connected between said first logic block at the data transfer source and said second logic block at the data transfer destination. The first logic block at the data transfer source transfers data to the second logic block at the transfer destination via the data line and transfers a clock signal unique for the first logic block to the second logic block at the transfer destination via the clock line. The second logic block of the data transfer destination includes a synchronization circuit that synchronizes data transmitted via the data line with the clock signal unique to the second logic block, using a clock signal transmitted via the clock line and a clock signal unique to the second logic block.
In this configuration, the range over which the operation synchronized with the clock signal is required can be restricted within each logic block. Hence, the clock skew can be reduced, compared with the case where the whole circuit on a semiconductor chip operates in sync with one clock signal. As a result, the operational speed of the semiconductor integrated circuit can be operated at high operational rate.
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Cho James H.
Young & Thompson
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