Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2005-02-01
2010-11-23
Payne, David C (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
Reexamination Certificate
active
07839966
ABSTRACT:
Sampling and analysis of input data is implemented within the programmable logic resource without using external equipment. CDR circuitry can be set to reference clock mode. In this mode, a reference clock signal is multiplied by a factor to generate a sample rate. The sample rate is divided by another factor, the desired width of the sampled data, to generate an output clock. The input data is sampled at the sample rate and sent to core circuitry based on the output clock. Dedicated circuitry in the core circuitry is configured to perform analysis on the sampled data.
REFERENCES:
patent: 5548249 (1996-08-01), Sumita et al.
patent: 5787114 (1998-07-01), Ramamurthy et al.
patent: 6314145 (2001-11-01), van Driest
patent: 6463092 (2002-10-01), Kim et al.
patent: 6480315 (2002-11-01), Brown
patent: 6483886 (2002-11-01), Sung et al.
patent: 6650140 (2003-11-01), Lee et al.
patent: 6724328 (2004-04-01), Lui et al.
patent: 6854044 (2005-02-01), Venkata et al.
patent: 6952431 (2005-10-01), Dally et al.
patent: 7133648 (2006-11-01), Robinson et al.
patent: 7143323 (2006-11-01), Sweet
patent: 7224951 (2007-05-01), Chuang et al.
patent: 2001/0033188 (2001-10-01), Aung et al.
patent: 2003/0052709 (2003-03-01), Venkata et al.
patent: 2004/0131058 (2004-07-01), Ghiasi
patent: 2004/0236977 (2004-11-01), Kizer et al.
patent: 2005/0028050 (2005-02-01), Ganry
patent: 2005/0111536 (2005-05-01), Cranford et al.
patent: 2005/0228605 (2005-10-01), Ribo
patent: 2005/0286669 (2005-12-01), Buchwald et al.
patent: 2006/0107154 (2006-05-01), Bansal et al.
Kossel et al., “Jitter Measurements of High-Speed Serial Links”, IEEE Design and Test of Computers, vol. 21, Issue 6, Nov.-Dec. 2004, pp. 536-543.
U.S. Appl. No. 10/059,014, filed Jan. 29, 2002, Lee et al.
U.S. Appl. No. 10/273,899, filed Oct. 16, 2002, Venkata et al.
U.S. Appl. No. 10/349,541, filed Jan. 21, 2003, Venkata et al.
U.S. Appl. No. 10/454,626, filed Jun. 3, 2003, Lui et al.
U.S. Appl. No. 10/637,982, filed Aug. 8, 2003, Venkata et al.
U.S. Appl. No. 10/668,900, filed Sep. 22, 2003, Asaduzzaman et al.
U.S. Appl. No. 10/713,877, filed Nov. 13, 2003, Churchill et al.
U.S. Appl. No. 10/741,593, filed Dec. 18, 2003, Kabani et al.
Altera Corporation, “Using Source-Synchronous Signaling with DPA in Stratix GX Devices,” Application Note 236, Version 1.0, Nov. 2002, pp. 1-18.
Altera Corporation
Jackson Robert R.
Panwalkar Vineeta S
Payne David C
Ropes & Gray LLP
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