Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2002-07-24
2004-08-24
Chin, Stephen (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C341S100000, C710S071000
Reexamination Certificate
active
06782067
ABSTRACT:
TECHNICAL FIELD
The invention relates to a data reception circuit for receiving a serial input data stream with a very high data transfer rate.
BACKGROUND ART
DE 689 19 211 T2 describes a receiver for serial data. The receiver contains shift registers into which samples of a data bit stream are read. The sample points are separated from one another by no more than half a data bit period. A decoder evaluates the samples which the shift register contains.
DE 195 29 690 A1 describes a microcomputer. The microcomputer contains a serial input/output circuit for outputting data, with parallel data being converted into serial data, and serial input data being converted into parallel data. The microcomputer contains a built-in serial input/output circuit having a clock signal supply device for applying a transfer clock signal to the serial input/output circuit. The microcomputer also contains an initialization device for initializing the clock supply device on the basis of a signal from an external circuit.
DE 690 25 510 T2 describes an asynchronous high-speed data interface. The asynchronous interface is used for processing serial data frames which are transferred in synchronism by a first clock, the interface comprising a device provided for serial/parallel conversion of the data using a first clock. The interface also contains a data buffer and a device provided for filling the data buffer with the serial/parallel converted data. The asynchronous interface also contains a further device for processing the data from the buffer in synch with a second clock, which is asynchronous with respect to the first clock, the second device starting the processing operation before the first device has completed the filling operation.
With an increasing transfer rate, data or information are/is transferred via a transfer channel in shorter and shorter times. The higher the data transfer rate, the higher the circuit complexity for the data reception circuit for receiving the input data stream received at the high data transfer rate, however. Conventional data reception circuits, which can receive a serial input data stream with a very high data transfer rate, also have a high power consumption on account of their circuit complexity.
SUMMARY OF THE INVENTION
It is therefore the object of the present invention to produce a data reception circuit for receiving a serial input data stream with a high data transfer rate which has low circuit complexity.
The invention achieves this object by means of a data reception circuit having the features specified in patent claim
1
.
Other advantageous refinements of the inventive data reception circuit are specified in the subclaims.
The invention produces a data reception circuit for receiving a serial input data stream with a high data transfer rate, where the data reception circuit has:
a data stream separation circuit for separating the serial input data stream into a plurality of separate data streams with a reduced data transfer rate,
a reference clock signal generation circuit for generating a reference clock signal whose clock frequency corresponds to the data transfer rate of the separate data streams,
a delay circuit having a delay element chain which comprises a plurality of series-connected delay elements, the first delay element in the delay element chain receiving the generated reference clock signal, and each delay element outputting a delayed reference clock signal via a signal output in the delay circuit,
a first, asynchronously clocked register array which comprises a plurality of register banks, each register bank in the first register array being asynchronously clocked by an associated separate data stream and reading in the delayed reference clock signals from the delay element chain in order to buffer-store a signal change in the separate data stream,
a second, synchronously clocked register array which comprises a plurality of register banks, each register bank in the second register array being synchronously clocked by the reference clock signal and reading in and buffer-storing the register content of an associated register bank in the first register array, and
a synchronously clocked logic circuit which evaluates the register content buffer-stored in the second register array in order to reconstruct the serial input data stream.
One advantage of the inventive data reception circuit is that the data stream separation circuit has a very small input capacity, and hence an input signal with a very high data frequency can be received by the inventive data reception circuit. This means that it is possible to receive a serial input data stream with a very high data transfer rate of, by way of example, 10 Gbit/sec.
Another advantage of the inventive data reception circuit is that it is not the received high-frequency input signal that is routed via the delay element chain in the delay circuit, as in conventional receiver arrangements, but rather a relatively low-frequency reference clock signal, which results in significantly reduced interference in the data reception circuit through “pattern noise”. With pattern noise interference, the irregular data signal received interferes with itself. Pattern noise cannot arise in the inventive data reception circuit, since the reference clock signal applied to the delay element chain is a regular, relatively low-frequency signal.
Another advantage of the inventive data reception circuit is that the circuit structure of the data reception circuit can be of modular design comprising similar modules, and hence is easy to implement and integrate in terms of circuitry.
Another advantage of the inventive data reception circuit is that the synchronously clocked logic circuit for reconstructing the serial input data stream can be implemented with automatic synthesis (VHDL), so that simple transfer to other technologies with little development complexity is ensured.
In one preferred embodiment of the inventive data reception circuit, each register bank in the first, asynchronously clocked register array has a first register for buffer-storing a rising signal edge in the associated separate data stream, and a second register for buffer-storing a falling signal edge in the associated separate data stream.
In one preferred embodiment of the inventive data reception circuit, each register bank in the second, synchronously clocked register array has two registers which read in the register content of the two registers in the associated register bank with in the first register array upon a rising signal edge in the reference clock signal.
The registers in the first register array and in the second register array preferably comprise a plurality of edge-triggered D-type flip-flops.
The number of edge-triggered D-type flip-flops in the registers in the first register array and in the second register array is preferably equal to the number of series-connected delay elements in the delay element chain.
The clock inputs of the D-type flip-flops in the first registers in all the register banks within the first, asynchronously clocked register array preferably receive a separate data stream which is output by the data stream separation circuit.
The clock inputs of the D-type flip-flops in the second registers in all the register banks within the first, asynchronously clocked register array preferably receive, in inverted form, a separate data stream which is output by the data stream separation circuit.
The data inputs of the D-type flip-flops in the first register and in the second register in a register bank in the asynchronously clocked first register array are preferably connected to an associated signal output in the delay circuit.
The clock inputs of the D-type flip-flops in the registers in all the register banks within the second, synchronously clocked register array, preferably receive the generated reference clock signal.
The data inputs of the D-type flip-flops in the first register in a register bank in the second, synchronously clocked register array are preferably connected to data outputs of the D-type flip-flo
Chin Stephen
Infineon - Technologies AG
Jenkins & Wilson & Taylor, P.A.
Perilla Jason M.
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