Asynchronous data holding circuit

Details Asynchronous data holding circuit Asynchronous data holding circuit

2011-05-03

2011-05-03

Connolly, Mark (Department: 2115)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C713S400000

Reexamination Certificate

active

07937607

ABSTRACT:
An asynchronous data holding circuit including a source synchronizer which acquires an enable signal synchronized with a destination clock, in response to a rising or falling edge of the enable signal, acquires the other one of the rising or falling edge of the enable signal in synchronization with a source clock, and outputs the enable signal, a first data holding unit which holds a data signal from the source, in response to the enable signal from the source synchronizer and the source clock, a destination synchronizer which outputs the enable signal from the source synchronizer, in synchronization with the destination clock, and a second data holding unit which holds the data signal in the first data holding unit in response to the enable signal from the destination synchronizer and the destination clock, is provided.

REFERENCES:
patent: 2001/0042219 (2001-11-01), Robertson
patent: 2002/0199124 (2002-12-01), Adkisson
patent: 2009/0271651 (2009-10-01), Pothireddy et al.
patent: 11-103238 (1999-04-01), None

Affiliated with

Also associated with

Rating

Asynchronous data holding circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Asynchronous data holding circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asynchronous data holding circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2681573