Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-08-26
2002-03-26
Pham, Chi (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C365S189050, C714S719000
Reexamination Certificate
active
06363132
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an asynchronous data conversion system. More particularly, this invention relates to an asynchronous data conversion system which causes an input data synchronous with one clock to be synchronized with another clock and output, in a digital circuit which operates by using, two kinds of asynchronous clocks.
Description of the Related Art
In the Japanese Patent Application Laid-Open No. HEI 8-237232, by way of conventional technology, a data change circuit is disclosed. The data change circuit comprises a data detecting section for causing input data to be synchronized with the reception clock to be latched to D-type flip-flop, and a data change section for causing the output thereof to be latched to D-type flip-flop by a transmission clock. The data change circuit also comprises a data change timing generating section, and a data change timing synchronizing section. The output of the data change section is taken to be output data, and the enable input signal of respective D-type flip-flops is controlled by the data change timing generating section and the data change timing synchronizing section.
In one example (embodiment 5) of this data change circuit, when the difference between two kind of clocks is sufficiently large, judging whether or not the same detected data continues to appear during the period corresponding to a plurality of clock cycles, while monitoring detected data synchronous with the master clock for the sake of a transmission clock during fixed time interval, and thus it enables the detected data to be changed by using transmission clock without generation of data change timing from the reception clock, caused by generation of the timing pulse which indicates the timing not existing change point of the detected data and which is synchronized with the master clock.
Further, in another example (embodiment 3) thereof, when both of a reception clock and a transmission clock are unknown, there is provided with a clock frequency comparison means, and a data change timing generating means, wherein the data change timing generating means controls pulse width of a data change timing pulse while receiving clock width binary data outputted from the clock frequency comparison means.
On the other hand, in the Japanese Patent Application laid-Open No. HEI 3-268530, which causes two kinds of a first and a second clocks to be prepared, thus latching an input data by the first clock, and latching output thereof by the second clock. Then in the output timing, there is observed both of the timing of the first clock and the timing of the second clock, thus outputting data which does not overlap with transmission latch timing pulse (which meets both of set up time and hold time). Thus, the data change method of asynchronous circuit is disclosed.
However, according to such conventional technology, after one of the data is inputted, before outputting data to the output side accurately or before receiving data outputted by the output side, when the second data is inputted, the output data is updated to the second data, with the result that lack of the data occurs.
Further, in cases where read-out is implemented before the output data is prepared, there is the possibility that prior data by one is outputted repeatedly, however there is not provided the function to detect the error.
The embodiment 5 described in the above Japanese Patent Application Laid-Open No. HEI 8-237232 has good conversion efficiency, when the difference between two kinds of clocks is sufficiently large, while when difference of the clock is obscure, it is incapable of using it. On the other hand, according to the embodiment
3
described in the gazette, there is no such the matter, however, conversion efficiency is inferior.
SUMMARY OF THE INVENTION
In view of the foregoing, it is an object of the present invention to provide an asynchronous data conversion system which is capable of preventing lack of data or redundancy of data and if lack or redundancy occurs, it is capable of detecting by way of error, and because it causes operation mode to be switched in relation to the case either difference of speed of two kind of clocks is sufficiently large or another case, the asynchronous data conversion system is capable of securing high conversion efficiency and high reliability without influence of size of difference of the clock.
In one arrangement to be described below by way of example in illustration of the present invention, an asynchronous data conversion system wherein input data is written in a latching section synchronously with a write clock in accordance with a write enable signal, subsequently the written data is read-out synchronously with a read clock which is asynchronous with the write clock, in accordance with a read enable signal, the asynchronous data conversion system comprises a ready signal generating section which generates a write ready signal with a writing to the latching section as holding state, and a read ready signal with a reading-out from the latching section as holding state synchronously with the write clock from the state relationship of HIGH/LOW in between the write enable signal and the read enable signal.
In another arrangement to be described by way of example in illustration of the present invention, an asynchronous data conversion system wherein input data is written in a latching section synchronously with a write clock in accordance with a write enable signal, subsequently the written data is read-out synchronously with a read clock which is asynchronous with said write clock, in accordance with a read enable signal, the asynchronous data conversion system comprises a ready signal generating section which generates a write ready signal with the writing to the latching section as holding state, and a read ready signal with the reading-out from the latching section as holding state synchronously with the write clock from state relationship of HIGH/LOW in between the write enable signal and the read acknowledge signal, and a read acknowledge signal generating section which generates the acknowledge signal synchronously with the read clock from the state relationship of HIGH/LOW in between the read enable signal and the read ready signal.
In yet another arrangement to be described below by way of example in illustration of the present invention, an asynchronous data conversion system wherein input data is written in a latching section synchronously with a write clock in accordance with a write enable signal, subsequently the written data is read-out synchronously with a read clock which is asynchronous with said write clock in accordance with a read enable signal, the asynchronous data conversion system comprises a ready signal generating section which generates a write ready signal with the writing to the latching section as holding state, and a read ready signal with the reading-out from the latching section as holding state synchronously with the write clock from the state relationship of HIGH/LOW in between the write enable signal and the read acknowledge signal, and a read acknowledge signal generating section which generates the acknowledge signal synchronously with the read clock from the state relationship of HIGH/LOW in between the read enable signal and the read ready signal.
In one particular arrangement to be described below by way of example in illustration of the present invention, the asynchronous data conversion system described above further comprises a write error detecting section which outputs a write error signal synchronously with the read clock depending on a state relationship of HIGH/LOW in between a write enable signal and a write ready signal, and a read error detecting section which outputs a read error signal synchronously with a read clock depending on a state relationship of HIGH/LOW in between a read enable signal and a read ready signal.
The above and further objects and novel features of the invention will be more fully understood from the following detailed description when the sa
Bayard Emmanuel
Ostrolenk Faber Gerb & Soffen, LLP
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