Asynchronous crossbar with deterministic or arbitrated control

Details Asynchronous crossbar with deterministic or arbitrated control Asynchronous crossbar with deterministic or arbitrated control

2007-10-16

2007-10-16

Pham, Brenda (Department: 2616)

Multiplex communications

Channel assignment techniques

Arbitration for access to a channel

C370S359000

Reexamination Certificate

active

10136025

ABSTRACT:
Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an output channel corresponds to one of a plurality of links. The crossbar circuitry is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information. Events on different links are uncorrelated.

REFERENCES:
patent: 4475188 (1984-10-01), Wilson et al.
patent: 4482996 (1984-11-01), Wilson et al.
patent: 4680701 (1987-07-01), Cochran
patent: 4773066 (1988-09-01), Kirkman
patent: 4849751 (1989-07-01), Barber et al.
patent: 4875224 (1989-10-01), Simpson
patent: 4912348 (1990-03-01), Maki et al.
patent: 5367638 (1994-11-01), Niessen et al.
patent: 5434520 (1995-07-01), Yetter et al.
patent: 5440182 (1995-08-01), Dobbelaere
patent: 5450549 (1995-09-01), Casparian
patent: 5479107 (1995-12-01), Knauer
patent: 5517495 (1996-05-01), Lund et al.
patent: 5572690 (1996-11-01), Molnar et al.
patent: 5666532 (1997-09-01), Saks et al.
patent: 5732233 (1998-03-01), Klim et al.
patent: 5752070 (1998-05-01), Martin et al.
patent: 5802055 (1998-09-01), Krein et al.
patent: 5802331 (1998-09-01), Van Berkel
patent: 5832303 (1998-11-01), Murase et al.
patent: 5889919 (1999-03-01), Inoue et al.
patent: 5918042 (1999-06-01), Furber
patent: 5920899 (1999-07-01), Chu
patent: 5949259 (1999-09-01), Garcia
patent: 5973512 (1999-10-01), Baker
patent: 6002861 (1999-12-01), Butts et al.
patent: 6038656 (2000-03-01), Martin et al.
patent: 6044061 (2000-03-01), Aybay et al.
patent: 6052368 (2000-04-01), Aybay
patent: 6072772 (2000-06-01), Charny et al.
patent: 6152613 (2000-11-01), Martin et al.
patent: 6230228 (2001-05-01), Eskandari et al.
patent: 6279065 (2001-08-01), Chin et al.
patent: 6301630 (2001-10-01), Chen et al.
patent: 6301655 (2001-10-01), Manohar et al.
patent: 6327253 (2001-12-01), Frink
patent: 6374307 (2002-04-01), Ristau et al.
patent: 6381692 (2002-04-01), Martin et al.
patent: 6502180 (2002-12-01), Martin et al.
patent: 2002/0021694 (2002-02-01), Benayoun et al.
patent: WO9207361 (1992-04-01), None
U.S. Appl. No. 09/501,638, filed Feb. 10, 2000, entitled, “Reshuffled Communications Processes in Pipelined Asynchronous Circuits”.
Lee et al., “Crossbar-Based Gigabit Packet Switch with an Input-Polling Shared Bus Arbitration Mechanism”, Sep. 21, 1997, XVI World Telecom Congress Proceedings, Interactive Session 3—Systems Technology & Engineering, pp. 435-441.
Ghosh et al., “Distributed Control Schemes for Fast Arbitration in Large Crossbar Networks”, Mar. 1994, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2, No. 1, pp. 55-67.
Andrew Matthew Lines,Pipelined Asynchronous Circuits, Jun. 1995, revised Jun. 1998, pp. 1-37.
Alain J. Martin,Compiling Communicating Processes into Delay-Insensitive VLSI Circuits, Dec. 31, 1985, Department of Computer Science California Institute of Technology, Pasadena, California, pp. 1-16.
Alain J. Martin,Erratum: Synthesis of Asynchronous VLSI Circuits, Mar. 22, 2000, Department of Computer Science California Institute of Technology, Pasadena, California, pp. 1-143.
U.V. Cummings, et al.An Asynchronous Pipelined Lattice Structure Filter, Department of Computer Science California Institute of Technology, Pasadena, California, pp. 1-8.
Alain J. Martin, et al.The Design of an Asynchronous MIPS R3000 Microprocessor, Department of Computer Science California Institute of Technology, Pasadena, California, pp. 1-18.
Venkat et al., “Timing Verification of Dynamic Circuits”, May 1, 1995, IEEE 1995 Custon Integrated Circuits Conference.
Wilson, “Fulcrum IC heats asynchronous design debate”, Aug. 20, 2002, http://www.fulcrummicro.com/press/article—eeTimes—08-20-02.shtml.
Martin, “Asynchronous Datapaths and the Design of an Asynchronous Adder”, Department of Computer Science California Institute of Technology, Pasadena, California, pp. 1-24.
Martin, “Self-Timed FIFO: An Exercise in Compiling Programs into VLSI Circuit”, Computer Science Department California Institute of Technology, pp. 1-21.

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