Asynchronous coupling and decoupling of chips

Details Asynchronous coupling and decoupling of chips Asynchronous coupling and decoupling of chips

2005-06-14

2005-06-14

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S009000, C326S021000

Reexamination Certificate

active

06906549

ABSTRACT:
In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The control circuitry selects an impedance level for the first and second resistive structures, and detect coupling of a remote receiver to the transmitter through interconnects and detect decoupling of the remote receiver from the transmitter. Other embodiments are described and claimed.

REFERENCES:
patent: 5374861 (1994-12-01), Kubista
patent: 5418475 (1995-05-01), Otaka
patent: 5821798 (1998-10-01), Tonn, Jr.
patent: 6130795 (2000-10-01), Freitas et al.
patent: 6222388 (2001-04-01), Bridgewater, Jr.
patent: 6424169 (2002-07-01), Partow et al.
PCI Express Base Specification Rvision 1.0, Jul. 22, 2002, cover page and pp. 4 and pp. 155-220.

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