Asynchronous circuit responsive to changes in logic level

Details Asynchronous circuit responsive to changes in logic level Asynchronous circuit responsive to changes in logic level

1980-04-11

1982-06-29

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Sync/clocking

307464, G11C 800

Patent

active

043375251

ABSTRACT:
An integrated circuit operable with low power consumption and high reliability is disclosed. The circuit comprises a logic circuit receiving an input logic signal at its input, detection means for detecting a change in the logic input signal, means responsive to an output of detection means for producing a control signal, and control means responsive to the control signal for setting the logic circuit at a predetermined condition irrespective of the input logic signal.

REFERENCES:
Hultman, "Memory Clock Design", IBM Tech. Disc. Bul., vol. 9, No. 10, 3/67, pp. 1328-1329.
Boudon et al., "Device for Suppressing the Clock Control in a Memory Using SGPL Cells", IBM Tech. Disc. Bul., vol. 21, No. 6, 11/78, pp. 2367-2368.

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