Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2001-10-05
2002-11-05
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S009000, C326S014000
Reexamination Certificate
active
06476643
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior French Patent Application No. 00 12826, filed on Oct. 6, 2000, the entire disclosure of which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an asynchronous circuit with a micro-pipeline type execution structure for detecting and correcting soft error in digital integrated circuits. It also relates to an implementation method.
2. Description of the Prior Art
In integrated logic circuits a soft error is a non-recurring event that disturbs the signal at a particular time. This type of disturbance, which is of extremely short duration, causes unwanted changes in the signal emitted by one or more logic gates of the digital integrated circuit. Such disturbances are caused particularly by alpha particles radiation. A logic circuit affected by alpha particles undergoes a sudden change in the logic status of its output terminal. Soft error can be also caused by events such as electromagnetic phenomena, etc.
It has hitherto been known in the art to detect and treat soft error on the output of a logic calculation unit of synchronous circuits in which the operation is governed by the appearance of a particular event such as a clock signal. A variety of methods have been used to ensure that the signal output by a logic calculation unit is not affected by soft error.
One of these methods consists in using a majority logic circuit in which the input terminals are connected to the output terminal of the logic calculation unit via a sampling circuit. The output signal of the logic calculation unit is sampled at three different times: t, t+d and t+2d. The time needed to perform the three samplings must be greater than at least twice the maximum duration of a potential soft error in order to be sure of producing a correct output signal. The three sampled signals are applied to the input terminals of the majority logic circuit. This majority logic circuit selects the logic signal with the greatest probability of being correct when one of the sampled signals provides a signal that is different from the two others and can thereby be used to check the operation of the logic calculation unit.
If the three input terminals of the majority logic circuit have the same status it is highly unlikely that the logic calculation unit has committed an error during the time taken to effect the three samples. The output of the majority logic circuit thus has the same status as that of the three inputs and thus transmits the logic signal supplied by the logic calculation unit.
If, on the other hand, any two of the inputs of the majority logic circuit have the same logic status and the third input has a different logic status, it is unlikely that the logic calculation unit has committed the same error twice during the time taken to effect the three samples and that it has functioned correctly for the sampled output applied to the third input of the majority logic circuit. The samples with the same logic status are thus in the majority and consequently the output of the majority logic circuit adopts the same logic status to transmit the signal.
This method, which combines a circuit that samples a signal output by a logic calculation unit with a majority logic circuit, uses a temporal redundancy to process the soft error in synchronous integrated circuits. This method is based on the fact that the duration of the soft error is known.
Other methods for processing soft error are used in synchronous circuits. One such method, rather than using a temporal redundancy, uses a total or partial hardware redundancy by adding another logic calculation unit in addition to that to be checked and compares their output signals.
Nevertheless, there are a certain number of drawbacks to these methods for checking soft error in synchronous circuits.
Firstly, methods which use a hardware redundancy involve increases in costs that are unacceptable when such products are intended for industry producing mass consumer electronics.
There are also drawbacks to methods for checking soft error based on temporal redundancy. On the one hand, they increase the time required to pass through the logic path by adding a duration greater than twice the duration of the soft error.
On the other, when the logic calculation unit is performing a large number of logic operations the duration of the soft error may not be easy to establish. An error that disturbs the signal output by the logic calculation unit with a maximum duration that is normally of the order of a few hundred picoseconds then propagates and its impact at the end of a long logic path may transform a pulse measuring one hundred picoseconds into a pulse measuring one nanosecond due to the different propagation times of the different electrical paths. Therefore when large logic calculation units are used, methods for correcting soft error in synchronous circuits based on the type of temporal redundancy described above are difficult to implement, particularly where sampling is concerned, because the duration of the soft error may be variable.
Lastly, it is not possible in synchronous circuits to recalculate the correct value output by the logic calculation unit on the fly. When an error is detected in the signal on output of a logic calculation unit the entire instruction must be performed, which wastes time.
Until now soft error was only detected and processed in synchronous circuits. Asynchronous circuits operating as micro-pipelines were not protected against soft error because such circuits are still very little used in integrated circuits. In pipeline-asynchronous operating modes the lack of a clock signal to time the performance of instructions, the performance of instructions is broken down more than in synchronous operating modes.
FIG. 1
shows a succession of logic stages E
0
, E
1
, E
2
of a micro-pipeline type asynchronous circuit of the prior art. Each logic stage E
0
, E
1
, E
2
has the same structure. Thus logic stages E
0
, E
1
, E
2
each include a logic calculation unit respectively numbered
9
,
1
and
5
, storage means composed of a latch circuit respectively numbered
10
,
2
and
6
, a control unit respectively numbered
11
,
3
and
7
, and a delay line respectively numbered
12
,
4
and
8
. The description states that a logic stage of an asynchronous circuit of the prior art will be considered with reference to FIG.
2
.
The control unit
3
of logic stage E
1
receives a signal Aout sent by control unit
7
of the next logic stage E
2
, together with a signal Rin sent by control unit
11
of the previous stage E
0
, both received via delay line
12
. Control unit
3
of logic stage E
1
is also provided to transmit a signal Rout to control unit
7
of the next logic stage E
2
, together with a signal Ain to control unit
11
of the previous stage E
0
.
Logic stages E
0
, E
1
and E
2
communicate using a local check. The operation of asynchronous circuits is based on the propagation of data and the use of a communication protocol that is used with request and acknowledgement signals. Thus logic stages E
0
, E
1
and E
2
, and more particularly their respective control units
11
,
3
and
7
, interact by means of signals Rin and Rout, known as request signals, and signals Ain and Aout, known as acknowledgement signals.
FIG. 2
shows a standard micro-pipeline type asynchronous architecture of the prior art and particularly shows the logic stage El of FIG.
1
. The same references are used for components already described with reference to FIG.
1
.
Logic calculation unit
1
supplies an output signal Din that is applied to the input terminal of the storage means consisting of latch circuit
2
. Latch circuit
2
transmits an output signal Dout that is applied to the logic calculation unit
5
of the next logic stage E
2
. Latch circuit
2
is controlled by control unit
3
using a data capture signal Lt. Control unit
3
receives the signals Rin and Aout and transmits signals
Hugues Jean-Francois
Vivet Pascal
Fleit Kain Gibbons Gutman & Bongini P.L.
Gutman Jose
Jorgenson Lisa K.
STMicroelectronics S.A.
Tokar Michael
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