Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Patent
1996-12-27
1998-06-02
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
711168, 711169, 711150, 711127, 395873, 395878, 395872, G06F 1316, G06F 938
Patent
active
057617287
ABSTRACT:
An asynchronous access system for a computer system includes processing modules performing processes, at least one shared system memory module, and a system bus connecting the processing modules and the shared system memory module. Each of the processing modules includes a processor, a plurality of buffers coupled to the processor and to the system bus, and a controlling unit for writing data from the plurality of processors into the shared system memory module. Data is written into the shared system memory module by a processor generating write instructions to write data via the plurality of buffers and the system bus. The controlling unit controls the writing such that one writing instruction writes data into a plurality of buffers, then transfers the data to the shared system memory module via the system bus, with another writing instruction writing additional data into another plurality of buffers and transferring the additional data to the shared system memory module.
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Funaki Jun
Kabemoto Akira
Saito Hiroshi
Sasaki Takatsugu
Sugahara Hirohide
Fujitsu Limited
Peikari J.
Swann Tod R.
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