Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-06-20
2002-11-19
Nguyen, Cuong Quang (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S900000
Reexamination Certificate
active
06483157
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the manufacture of an integrated circuit and, more particularly, to the formation of an n-channel and/or p-channel asymmetrical transistor having a gate oxide incorporated with barrier atoms to enhance transistor performance.
2. Description of the Related Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline (“polysilicon”) material over a relatively thin gate oxide. The polysilicon material and gate oxide is then patterned to form a gate conductor formed laterally between exposed regions of single crystalline silicon substrate. The gate conductor and exposed substrate regions are then implanted with an impurity dopant material. If the impurity dopant material used for forming the junction areas within the exposed substrate is n-type, then the resulting MOSFET is an NMOSFET (“n-channel”) transistor device. Conversely, if the dopant material is p-type, then the resulting MOSFET is a PMOSFET (“p-channel”) transistor device.
The gate conductor and adjacent implant areas (herein “junctions”) are formed using well known photolithography and ion implant techniques. Gate conductors and implant regions arise in openings formed through a thick dielectric layer of what is commonly referred to as field oxide. Those openings and the transistors formed therein are termed active regions. The active regions are therefore regions between field oxide regions. Metal interconnect is routed over the field oxide to couple with the polysilicon gate conductor as well as with the junction to complete the formation of an integrated circuit.
Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single monolithic substrate. While both types of devices can be formed, the devices are distinguishable based on the dopant species used. The method by which n-type dopant is used to form an n-channel device and p-type dopant is used to form a p-channel device entails unique problems associated with each device. As layout densities increase, the problems are exacerbated. Device failure can occur unless adjustments are made to processing parameters and processing steps. N-channel processing must, in most instances, be dissimilar from p-channel processing due to the unique problems of n-channel transistors relative to each type of device.
N-channel devices are particularly sensitive to so-called short-channel effects (“SCE”). The distance between a source-side junction and a drain-side junction is often referred to as the physical channel length. However, after implantation and subsequent diffusion of the junctions, the actual distance between junctions becomes less than the physical channel length and is often referred to as the effective channel length (“Leff”). In VLSI designs, as the physical channel becomes small, so too must the Leff. SCE becomes a predominant problem whenever Leff drops below, e.g., 2.0 &mgr;m.
Generally speaking, SCE impacts device operation by, inter alia, reducing device threshold voltages and increasing sub-threshold currents. As Leff becomes quite small, the depletion regions associated with the source and drain areas within the junctions may extend toward one another and substantially occupy the channel area. Hence, some of the channel will be partially depleted without any influence of gate voltage. As a result, less gate charge is required to invert the channel of a transistor having a short Leff. Somewhat related to threshold voltage lowering is the concept of sub-threshold current flow. Even at times when the gate voltage is below the threshold amount, current between the source and drain nonetheless exist for transistors having a relatively short Leff.
Two of the primary causes of increased sub-threshold current are: (i) punch through and (ii) drain-induced barrier lowering (“DIBL”). Punch through results from the widening of the drain depletion region when a reverse-bias voltage is applied across the drain-well diode. The electric field of the drain may eventually penetrate to the source area, thereby reducing the potential energy barrier of the source-to-body junction. Punch through current is therefore associated within the substrate bulk material, well below the substrate surface. Contrary to punch through current, DIBL-induced current occurs mostly at the substrate surface. Application of a drain voltage can cause the surface potential to be lowered, resulting in a lowered potential energy barrier at the surface and causing the sub-threshold current in the channel near the silicon-silicon dioxide interface to be increased. One method in which to control SCE is to increase the dopant concentration within the body of the device. Unfortunately, increasing dopant within the body deleteriously increases potential gradients in the ensuing device.
Increasing the potential gradients produces an additional problems known as hot-carrier effect/injection (“HCI”). HCI is a phenomena by which the kinetic energy of the carriers (holes or electrons) is increased as they are accelerated through large potential gradients and subsequently become trapped within the gate oxide. The greatest potential gradient, often referred to as the maximum electric field (“Em”) occurs near the drain during saturated operation. More specifically, the electric field is predominant at the lateral junction of the drain adjacent the channel.
Using the n-channel example, the electric field at the drain causes channel electrons to gain kinetic energy. Electron-electron scattering randomizes the kinetic energy and the electrons become “hot”. Some of these hot electrons have enough energy to create electron-hole pairs through impact ionization of the silicon atoms. Electrons generated by impact ionization join the flow of channel electrons, while the holes flow into the bulk to produce a substrate current in the device. The substrate current is the first indication of the creation of hot carriers in a device. For p-channel devices, the fundamentals of the process are essentially the same except that the role of holes and electrons are reversed.
HCI occurs when some of the hot carriers are injected into the gate oxide near the drain-side junction, where they induce damage and become trapped. Traps within the gate oxide generally become electron traps, even if they are initially filled with holes. As a result, there is a negative charge density in the gate oxide. The trapped charge accumulates with time, resulting in positive threshold shifts in both n-channel and p-channel devices. It is known that since hot electrons are more mobile than hot holes, HCI causes a greater threshold skew in n-channel devices than p-channel devices. Nonetheless, a p-channel device will undergo negative threshold skew if its Leff is less than, e.g., 0.8 &mgr;m.
Unless modifications are made to the transistor structure, problems of sub-threshold current and threshold shift resulting from SCE and HCI will remain. To overcome these problems, alternative drain structures such as double-diffused drains (DDDs) and lightly doped drains (LDDs) must be used. The purpose of both types of structures is the same: to absorb some of the potential into the drain and thus reduce Em. The popularity of DDD structures has given way to LDD structures since DDD causes unacceptably deep junctions and deleterious junction capacitance.
A conventional LDD structure is one whereby a light concentration of dopant is self-aligned to the gate conductor followed by a heavier dopant self-aligned to the gate conductor on which two sidewall spacers have been formed. The purpose of the first implant dose is to produce a lightly doped section within the junction at the gate edge near the channel. The second implant dose is spaced from the channel a distance dictated by the thickness of the sidewall spacer. The second implant dose is the source/drain implant placed within the junction laterally outside the LDD area, also within the junction. Resu
Fulford H. Jim
Gardner Mark I.
Daffer Kevin L.
Nguyen Cuong Quang
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