Asymmetrical SRAM cell with 4 double-gate transistors

Details Asymmetrical SRAM cell with 4 double-gate transistors Asymmetrical SRAM cell with 4 double-gate transistors

2008-05-29

2010-06-08

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000

Reexamination Certificate

active

07733688

ABSTRACT:
The random access memory cell of SRAM type comprises an access transistor provided with a gate electrode connected to a word line. The access transistor is connected between a bit line and a gate electrode of a first load transistor itself connected to a gate electrode of a driver transistor and to a first source/drain electrode of a second load transistor. The first load transistor and the driver transistor, in series, form an inverter at the supply voltage terminals. At least the transistors not comprised in the inverter comprise two electrically independent gate electrodes. The second gate electrode of the access transistor is connected to the first gate electrode of the second load transistor and the second gate electrode of the latter is connected to the supply voltage.

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