Asymmetrical random access memory cell, memory comprising...

Details Asymmetrical random access memory cell, memory comprising... Asymmetrical random access memory cell, memory comprising...

2007-01-31

2009-02-24

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189050, C365S230060

Reexamination Certificate

active

07495949

ABSTRACT:
An asymmetrical random access memory cell (1) including cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistors (21, 31), wherein said cross coupled inverters (2, 3) have different switching thresholds and exhibit asymmetrical physical behaviours, wherein an additional pass-transistor (4) is provided in series to one of the pass-transistors (21) between one of the nodes (22) and its dedicated bit-line (blc). Further the invention relates to a random access memory including such memory cells and to a method of operating such a memory.

REFERENCES:
patent: 6111780 (2000-08-01), Bertin
patent: 7158402 (2007-01-01), Houston
patent: 1505607 (2005-02-01), None
Navid Azzi, Farid N. Najm, Andreas Moshovos, Low-Leakage Asymmetric-Cell SRAM, Aug. 2003, vol. 11 No. 4, IEEE, Canada.
Leland Chang, David M. Fried, Jack Hergenrother, Jeffrey W. Sleight, Robert H. Dennard, Robert K. Montoye, Lidija Sekaric, Shareee J. McNab, Anna W. Topoi, Charlotte D. Adams, Kathryn W. Guarini and Wilfried Haensch, Stable SRAM Cell Design for the 32 nm Node and Beyond, 2005 Symposium on VLSI Technology Digest of Technical Papers, T.J. Watson Research Center, New York.

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