Asymmetrical non-volatile memory cell, arrays and methods for fa

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257344, 365185, H01L 2978

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active

052025764

ABSTRACT:
A non-volatile memory cell (10) is formed in the face of a layer of semiconductor (12) of a first conductivity type, and includes a first heavily doped diffused region (14) and a second heavily doped diffused region (16) formed in semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type. First heavily doped diffused region (14) and second heavily doped diffused region (16) are spaced by a channel area (18). A first lightly doped diffused region (20) is formed adjacent first heavily doped diffused region (14) to be of the second conductivity type. A second lightly doped diffused region (22) is formed in semiconductor layer (12) adjacent second heavily doped diffused region (16) to be of the second conductivity type. A floating gate (24) insulatively overlies the channel area and insulatively overlies a selected one of lightly doped diffused regions (20,22). A control gate (30) insulatively overlies floating gate (24).

REFERENCES:
patent: 4652897 (1987-03-01), Okuyama et al.
patent: 4835740 (1989-05-01), Sato
patent: 4939558 (1990-07-01), Smayling
D. L. Geriach et al., "Reliability Failure Mechanisms", 1990 International Electron Devices and Materials Symposium, Nov. 14-16, 1990, pp. 273-280.

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