Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
1999-08-30
2001-09-25
Picardat, Kevin M. (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S678000, C257S666000, C257S787000, C438S106000
Reexamination Certificate
active
06294825
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to a method of electrical packaging devices. More particularly, the present invention relates to transfer molding of microelectronic devices using asymmetric encapsulation. In particular, the present invention relates to asymmetrically molding a plurality of chip-and-board pre-assemblies by arranging them into a multiple-part matrix.
2. The Relevant Technology
In the packaging of semiconductor chip assemblies, it has been found desirable to place encapsulation material in and around elements of the semiconductor chip. Encapsulation material helps to reduce and redistribute strain, stress, and damage between the semiconductor chip and the connections made therefrom. It also reduces strain, stress, and damage between the chip and supporting substrates such as printed circuit boards. Additionally, the encapsulation material seals the components against the elements as well as facilitates continued electrical contact between the semiconductor chip and the printed circuit board. Additionally, the encapsulation material may hold the entire semiconductor chip package together.
It is also preferred through packaging of semiconductor chips to be able to handle the chip package under commercial assembly conditions such as simultaneously-produced packages without causing damage thereto. However, if a semiconductor chip package assembly needs to be self-packaged, care must be taken during encapsulation to ensure that placement of the encapsulation material does not compromise the integrity of the terminals on the substrate such as a ball array and the like. In particular, it is important to avoid contacting the terminals on the substrate with the encapsulation material.
In the chip packaging field, miniaturization includes the process of crowding an increasing number of microelectronic circuits onto a single chip and simultaneously reducing the overall chip package size so as to achieve smaller and more compact devices. Examples of such devices include hand-held computers, personal data assistants, portable telecommunication devices and the like. Ideally, the size of the chip will continue to be miniaturized and the chip package size will continue to shrink until the chip package will be no larger than the chip itself.
As the overall chip package is subject to miniaturization, ball arrays have been reduced to less than I mm pitch. Miniaturization has the counterproductive effect upon chip packaging of an increased heat load per unit chip volume because of a denser electronic activity. This increased heat load must be borne by a smaller chip package structure. Miniaturization also has the counterproductive effect of increased thermal stresses upon the chip package due to increased thermal loads that lead to warping, and bowing of both chip and board, and circuit failure due to thermally stressed and broken electrical connections between chip and board.
Where a chip package is to be overmolded with an encapsulation material, overmolding of the chip package on both surfaces of a printed circuit board, also referred to as a substrate, previously required that the overmolded substrate have substantially the same projected area of mold material disposed upon each side thereof. The requirement of substantially the same projected area of mold material disposed upon each side of the substrate was due to the fact that mold cavities were symmetrical. Symmetrical mold cavities were required for many reasons. One reason was because of the viscosity inherent in encapsulation material during the overmolding process and the high degree of pressure that was required to hold a mold together at its seams in order to prevent encapsulation material from leaking between the mold seams and contaminating electrical contacts such as ball arrays.
Where chip packaging is preferably a high-volume process, the simultaneous overmolding of a chip on board package could not previously be done in a single molding operation due to the limiting nature of symmetrical mold cavities. In a symmetrical mold cavity using the transfer-molding method, the encapsulation material, typically a thermoplastic or a thermosetting material, enters into the mold cavity and flows over the integrated circuit chip. Flow also covers the electrical leads that are exposed within the mold cavity. The encapsulation material is then cured to harden it. Traditionally, it has been necessary to control the flow of the encapsulation material into the cavity for a number of reasons. Initially, a void-free fill over the integrated circuit chip was necessary so as to prevent exposure and contamination of the integrated circuit chip during subsequent handling and field use. Additionally, thermosetting fill material needed to be flowing into the mold cavity under conditions so as not to displace any material such as bond wires.
As the size of the chip package continues to shrink, the available real estate on the printed circuit board for making electrical connection to the chip comes at an increasing premium. Thus, methods of wiring chips to the board must be found to accommodate the shrinking amount of printed circuit board real estate.
There is therefore a need for an improved encapsulation method for transfer molding of electronic devices wherein an asymmetric overmolded design is achieved in a single molding operation where the encapsulation procedure is simultaneously performed on a multiple-part matrix of electrical device and substrate pre-assemblies simultaneously. Such multiple-part matrixes, asymmetrical molding apparatuses, and methods are disclosed and claimed herein.
SUMMARY OF THE INVENTION
The present invention relates to a multiple-part matrix asymmetrical mold tooling and a method of using it. The tooling is designed for simultaneous asymmetrical molding of a plurality of chip and board pre-assemblies. The tooling includes a first mold half. The first mold half has a plurality of unisolated depressions therein. Each unisolated depression is in flow communication with at least one other unisolated depression through either a runner channel or a header channel. The unisolated depressions are thus connected either in series, in parallel, or both.
The multiple-part matrix mold tooling further comprises a second mold half that matches the first mold half with a plurality of isolated depressions that correspond to the first mold half plurality of unisolated depressions. Each second mold half isolated depression is smaller in volume than its corresponding first mold half unisolated depression.
In one embodiment of the present invention, a first unisolated depression in the first mold half is in flow communication with a header channel and a runner channel on one edge thereof and with a runner channel on a second edge thereof. The header channel may be in flow communication with at least three first unisolated depressions or a greater number such as six. Where the header channel is in flow communication with more than three first unisolated depressions, it is preferable the plurality of first unisolated depressions is disposed on opposite sides of the header channel.
In one embodiment, a plurality of header channels is configured in flow communication with a plunger site. In this embodiment of the present invention, the plurality of first unisolated depressions may be supplied through a corresponding plurality of runners.
In accordance with a method embodiment of the present invention, the method includes forming at least one substrate having a plurality of package sites. To the plurality of package sites are attached a plurality of electrical devices to form a plurality of pre-assemblies. Each pre-assembly has a first surface and a second surface. The pre-assemblies are set into the inventive multiple-part matrix mold tooling. A first amount of encapsulation material is positioned on the first surface by transfer molding. The encapsulation material continues to flow through a plurality of gates, one gate for each pre-assembly, that is formed between slots in t
Bolken Todd O.
Johnson Mark S.
Collins D. M.
Micro)n Technology, Inc.
Picardat Kevin M.
Workman & Nydegger & Seeley
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