Asymmetrical memory cells and memories using the cells

Details Asymmetrical memory cells and memories using the cells Asymmetrical memory cells and memories using the cells

2011-03-08

2011-03-08

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S155000, C365S156000

Reexamination Certificate

active

07903450

ABSTRACT:
Asymmetrical SRAM cells are improved by providing one or more of improved read stability and improved write performance and margin. A first inverter and a second inverter are cross-coupled and configured for selective coupling to true and complementary bit lines under control of read and write word lines. The first inverter is formed by a first, n-type, FET (NFET) and a second, p-type, FET (PFET). Process and/or technology approaches can be employed to adjust the relative strength of the FETS to obtain, for example, read margin, write margin, and/or write performance improvements.

REFERENCES:
patent: 5673230 (1997-09-01), Kuriyama
patent: 5986924 (1999-11-01), Yamada
patent: 6198656 (2001-03-01), Zhang
patent: 6205049 (2001-03-01), Lien et al.
patent: 6573549 (2003-06-01), Deng et al.
patent: 6831483 (2004-12-01), Shimazaki et al.
patent: 7177177 (2007-02-01), Chuang et al.
patent: 7200030 (2007-04-01), Yamaoka et al.
patent: 7362606 (2008-04-01), Chuang et al.
patent: 7609542 (2009-10-01), Adams et al.
patent: 7626855 (2009-12-01), Kodama et al.
patent: 7710765 (2010-05-01), Hanafi
Chuang et al., U.S. Appl. No. 11/362,612, filed Feb. 27, 2006.
Chuang et al., U.S. Appl. No. 11/362,613, filed Feb. 27, 2006.
Azizi et al , “Low-Leakage Asymmetric-Cell SRAM,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, No. 4, pp. 701-715 (Aug. 2003).
Guo et al., “FinFET-Based SRAM Design,” ISLPED (Aug. 8-10, 2005).
Yamaoka et al., “Low Power SRAM Menu for SOC Application Using Yin-Yang-Feedback Memory Cell Technology,” Symposium on VLSI Circuits Digest of Technical Papers, pp. 288-291 (2004).
Kuriyama et al., “An Asymmetric Memory Cell using a C-IFT for ULSO SRAMs,” Symposium on VLSI Technology Digest of Technical Papers, pp. 38-39 (1992).
Itabashi et al., “A Split Wordline Cell for 16Mb SRAM Using Polysilicon Sidewall Contacts,” IEEE, IEDM 91 (1991).
“Taurus-Medici: Industry-standard device simulation tool,” Synopsys Data Sheet (2003).
Shang et al., “Mobility and CMOS Devices/Circuits on sub-10nm (110) Ultra Thin Body SOI,” Symposium on VLSI Technology Digest of Technical Papers, pp. 78-79 (2005).
Kim et al., “Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS,” Solid-State Electronics 48, pp. 239-243 (2004).
Takeda et al., “A Read-Stantic-Noise-Margin-Free SRAM Cell for Low-Vddand High-Speed Applications,” IEEE International Solid-State Circuits Conference, pp. 478-479, 611 (2005).

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