Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2005-09-19
2009-02-03
Connolly, Mark (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S400000, C713S600000, C711S100000
Reexamination Certificate
active
07487378
ABSTRACT:
An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.
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Wei-Zen Chen, et al., “A 2.5GBPS Serial-Link Data Transceiver in a 0.35 UM Digital CMOS Technology” 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC2004) Aug. 4-5, 2004, pp. 232-235.
Chen Lin
Gauthier Claude
Lee Ming-Ju E.
Macri Joseph
Morein Stephen
Abbaszadeh Jaweed A
ATI Technologies Inc.
Connolly Mark
Courtney Staniford & Gregory LLP
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