Asymmetric source/drain transistor employing selective...

Details Asymmetric source/drain transistor employing selective... Asymmetric source/drain transistor employing selective...

2007-05-22

2007-05-22

Nhu, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S192000, C257S213000, C257SE21008, C257S051000, C257S546000, C257S562000

Reexamination Certificate

active

11067410

ABSTRACT:
According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.

REFERENCES:
patent: 6261911 (2001-07-01), Lee et al.
patent: 6596594 (2003-07-01), Guo
patent: 6890823 (2005-05-01), Lee et al.
patent: 7002223 (2006-02-01), Kwon
patent: 7029989 (2006-04-01), Kim et al.
patent: 07-283410 (1995-10-01), None
patent: 1999-0081382 (1999-11-01), None
patent: 1999-0086528 (1999-12-01), None
English abstract of Korean Publication No. 1999-0086528.
English abstract of Korean Publication No. 1999-0081382.
English abstract of Korean Publication No. 07-283410.

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