Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-31
2003-12-23
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S299000, C438S302000, C438S306000, C257S335000, C257S345000
Reexamination Certificate
active
06667512
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to an asymmetric retrograde HALO Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).
2. Description of the Related Art
Constant advances in the art of microelectronic device fabrication have resulted in the realization of sub-quarter micron MOSFETs. As devices are scaled down to such small sizes, numerous problems emerge which require solution. A class of such problems is known in the art as “short channel effects”, one of which is punchthrough, which occurs when electric field lines from the drain extend toward the source and reduce the potential barrier height.
Numerous arrangements have been proposed to inhibit punchthrough and other short channel effects. A recent proposal is described in U.S. Pat. No. 5,917,219, entitled SEMICONDUCTOR DEVICES WITH POCKET IMPLANT AND COUNTER DOPING”, issued Jun. 29, 1999 to M. Nandakumar et al. This patent teaches how to form punchthrough inhibiting “HALO” implants or pockets under a MOSFET's source and drain where they abut the device's channel region.
The HALO regions have the same conductivity type as the device's channel (with a higher dopant concentration), and a conductivity type opposite to that of the device's source and drain. The opposite conductivity of the HALO pockets inhibit extension of the electric field lines from the drain toward the source and thereby punchthrough.
As MOSFETs have been scaled below quarter-micron channel lengths, background and channel doping have been raised to high levels to control short channel effects. This has led to reduced mobility and difficulty in obtaining a desired low threshold voltage. The above referenced patent to Nandakumar further teaches a response to this problem which involves providing a non-uniform channel profile with the peak of the concentration as close to the surface as possible while still maintaining a low surface concentration. This arrangement is used by Nandakumar in addition to the source and drain HALO implants.
Another proposal is described in a paper entitled “A New Asymmetrical Halo Source GOLD Drain (HS-GOLD) Deep Sub-Half-Micrometer n-MOSFET Design for Reliability and Performance”, by T. Buti et al, IEEE Transactions on Electron Devices, Vol. 38, No. 8, Pages 1757 to 1764. This paper teaches how to form an asymmetrical channel doping profile with a HALO implant only on the source side.
In MOSFET design, it is desirable to provide high drive current (saturation drain current I
dsat
) and transconductance g
m
, and low off-state leakage current I
doff
. Generally, any attempt to increase the drive current will produce a corresponding increase in off-state leakage current. This problem has heretofore limited the drive current in very short channel MOSFETs.
SUMMARY OF THE INVENTION
The present invention overcomes the problem which has existed in the prior art and limited the drive current in short channel MOSFETs. In accordance with the present invention, an asymmetric retrograde HALO Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) includes a semiconductor substrate. A gate is formed over the substrate, the gate defining a channel thereunder in the substrate having a source side and a drain side.
A retrograde HALO doped area is formed in the source side of the channel using tilted ion implantation. A source and drain are formed in the substrate adjacent to the source and drain sides of the channel. The asymmetrical doping arrangement provides the specified level of off-state leakage current without decreasing saturation drive current and transconductance.
These and other features and advantages of the present invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings, in which like reference numerals refer to like parts.
REFERENCES:
patent: 5780912 (1998-07-01), Burr et al.
patent: 5790452 (1998-08-01), Lien
patent: 5891782 (1999-04-01), Hsu et al.
patent: 5917219 (1999-06-01), Nandakumar et al.
patent: 5985727 (1999-11-01), Burr
patent: 5989963 (1999-11-01), Lunning et al.
patent: 6166410 (2000-12-01), Lin et al.
T. Buti et al., “A New Asymmetrical Halo Source GOLD Drain (HS-GOLD) Deep Sub-Half-Micrometer n-MOSFET Design for Reliability and Performance,” IEEE Transactions on Electron Devices, vol. 38, No. 8, Aug. 1991, pp. 1757-1764.
A. Hiroki et al., “A High Performance 0.1um MOSFET with Asymmetric Channel Profile,” International Electron Devices Meeting, Technical Digest, IEDM'95 (1995) 439-442.
Y. Taur et al., “CMOS Devices below 0.1 um: How High Will Peformance Go?,” International Electron Devices Meeting, Technical Digest, IEDM'97 (1997) 215-218.
S. Odanaka et al., “Potential Design and Transport Property of 0.1-um MOSFET with Asymmetric Channel Profile,” IEEE Transactions on Electron Devices, vol. 44, No. 44, Apr. 1997, pp. 595-600.
“Narrow Base Lateral PNP Bipolar Fabrication Using Angle Implant Technique,” IBM Technical Disclosure Bulletin, Dec. 1991, vol. 34, #7B, pp. 130-131.
Huster Carl R.
Riccobene Concetta
Advanced Micro Devices , Inc.
Dickey Thomas L
Tran Minh Loan
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