Asymmetric RAM cell

Details Asymmetric RAM cell Asymmetric RAM cell

2001-03-19

2002-03-26

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C257S903000

Reexamination Certificate

active

06363006

ABSTRACT:

FIELD OF INVENTION
The present invention relates generally to complementary metal oxide semiconductor (CMOS) static random access memories (SRAM), and more particularly to a single-ended read, differential write CMOS, SRAM cell including two inverters connected in a regenerative feedback circuit, wherein each inverter includes a pair of complementary field effect transistors (FETs), and FETs of the same type in each inverter have differing gate region widths and/or drive currents.
BACKGROUND ART
FIG. 1
is a block diagram of a prior art CMOS SRAM
10
including many memory cells. Each cell contains a pair of inverters connected in a regenerative feedback circuit. Each of the inverters includes two complementary FETs. The cells of SRAM
10
are addressed by word write/read logic network
12
, bit write logic network
14
, and bit read logic network
16
. Typically, SRAM
10
is a matrix of cells including M-words, each having N-bits, where M is 0, 1 . . . i . . . M, and N is 0, 1 . . . k . . . N; M and N are typically powers of two minus the quantity one, e.g., 255 and 1,023, respectively. Word write/read logic network
12
includes M output terminals, word
0
, word
1
. . . word
i
. . . word
M
, one of which is provided for each of the M words of SRAM
10
. Bit write logic network
14
includes N complementary output terminals, nbit
0
, nbit
1
. . . nbit
k
. . . nbit
N
and N non-complementary output bit terminals, bit
0
, bit
1
. . . bit
k
. . . bit
N
. Bit read logic network
16
includes N complementary input terminals, nbit
0
, nbit
1
. . . nbit
k
. . . nbit
N
and N non-complementary input terminals, bit
0
, bit
1
. . . bit
k
. . . bit
N
. The nbit and bit terminals with corresponding numbers of bit write logic network
14
and bit write logic network
16
are connected to identical vertically extending lines (i.e., leads) in SRAM
10
with line numbers corresponding to the terminal numbers so that, e.g., the nbit
k
terminal of write logic network
14
and the nbit
k
terminal of bit read logic network
16
are connected to the nbit
k
line of SRAM
10
, while bit
k
terminal of write logic network
14
and bit
k
terminal of read logic network
16
are connected to the bit
k
line of SRAM
10
.
FIG. 2
is a circuit diagram of the structure included in each cell of SRAM
10
. For purposes of illustration,
FIG. 2
is considered to be the cell at word
i
bit
k
. The cell of
FIG. 2
includes two inverters
20
and
22
, connected to each other in a regenerative, positive feedback circuit
24
. Inverter
20
includes complementary P-channel transistor
26
and N-channel transistor
28
having source drain paths connected in series between the chip positive DC power supply voltage (+V
DD
) and ground so that common drain terminals of FETs
26
and
28
are connected to terminal
30
. Similarly, inverter
22
includes P-channel FET
32
and N-channel FET
34
having series connected source drain paths connected together between +V
DD
and ground so that FETs
32
and
34
have a common drain connection at terminal
36
. The common drain terminal
30
of FETs
26
and
28
drives the gate electrodes of FETs
32
and
34
in parallel while the common drain terminal
36
of FETs
32
and
34
drives the gate electrodes of FETs
26
and
28
in parallel. Terminal
30
is selectively connected through the source drain path of N-channel pass gate FET
40
to nbit
k
line
42
, while the source drain path of N-channel pass gate FET
44
selectively connects terminal
36
to bit
k
line
46
. Word
i
line
48
drives the gate electrodes of FETs
40
and
44
in parallel.
The cell of
FIG. 2
was originally designed for differential read, differential write operation but has more recently been proposed for single-ended read, differential write operation. The widths and lengths of the dielectric regions of the gates of N-channel FETs
28
and
34
are the same, while the widths and lengths of the dielectric regions of the gates of P-channel FETs
26
and
32
are the same. Consequently, the gate widths and drive currents of FETs
26
and
36
are the same, while the gate widths and drive currents of FETs
28
and
34
are the same. In addition, the gate widths and gate capacitances of FETs
40
and
44
are the same because the lengths and widths of the dielectric regions of FETs
40
and
44
are the same. In a prior art configuration, the gate widths of N-channel FETs
28
and
34
are 0.36 &mgr;m, the gate widths of P-channel FETs
26
and
32
are 0.32 &mgr;m, and the gate widths of FETs
40
and
44
are 0.28 &mgr;m and all of FETs
26
,
28
,
32
,
34
,
40
and
44
have gate lengths of 0.16 &mgr;m.
When the cell of
FIG. 2
is written or read for single-ended operation, logic network
12
supplies a positive (+V
DD
) voltage to line
48
, while logic network
14
supplies signals to lines
42
and
46
, and read logic network
16
supplies enable signals to its input terminals connected to lines
42
and
46
as follows. Prior to logic network
12
supplying the positive voltage to word line
48
, write logic network
14
precharges one of nbit line
42
or bit line
46
to the positive voltage. To write a binary one into the cell of
FIG. 2
logic network
14
reduces the voltage on nbit line
42
to ground but precharges the voltage on bit line
46
high prior to logic network
12
applying a high voltage to word line
48
. FETs
40
and
44
are enabled by the positive voltage on line
48
to pass the low and high voltages on lines
42
and
46
to terminals
30
and
36
. The low and high voltages at terminals
30
and
36
cause turn on of FETs
28
and
32
and turn off of FETs
26
and
34
. Because of the regenerative connections of inverters
20
and
22
, FETs
28
and
32
stay on and FETs
26
and
34
stay off and the voltages at terminals
30
and
36
respectively remain low and high after logic network
12
reduces the voltage on word line
48
to turn off FETs
40
and
44
. Similarly, but in an opposite manner, logic network
14
writes a binary zero into the cell of
FIG. 2
by applying high and low precharge voltages to lines
42
and
46
, causing turn on of FETs
26
and
34
and turn off of FETs
28
and
32
in response to a positive voltage on write line
48
. Hence, terminals
30
and
36
are at high and low voltages as a result of the positive voltage on line
48
.
To read the binary value the cell of
FIG. 2
stores, read logic network
16
samples the voltage at terminal
36
by enabling an input terminal of a detection circuit (not shown) of the read logic network after line
46
has been precharged to a high (i.e., positive) voltage and while word write/read logic network
12
applies a high voltage to line
48
. If the cell of
FIG. 2
is storing a bit causing terminals
30
and
36
to be respectively at high and low voltages, the low voltage at terminal
36
pulls down the voltage on line
46
when the positive voltage on line
48
turns on FET
44
. The high voltage at terminal
36
causes line
46
to stay at a high voltage when the positive voltage on line
48
turns on FET
44
. The detection circuit connected to line
46
senses the low and high voltages on line
46
to indicate the binary value the cell of
FIG. 2
stores.
Because the memory of FIG.
1
and the cell of
FIG. 2
are read on a single ended basis, the voltage variations of pulses on nbit line
42
during a read operation are not detected by bit read logic network
16
. Consequently, a slow slew rate on nbit line
46
does not have a particularly adverse effect on read operations of the memory of FIG.
1
and the cell of FIG.
2
. (Slew rate is the time rate of change of the voltage of leading edges of the pulses.)
FIG. 3
is a top view of the actual physical layout of the cell schematically illustrated in FIG.
2
. The cell of
FIG. 3
is approximately rectangular, having a width of 2.22 &mgr;m, and a length of 2.52 &mgr;m., i.e., the distance between parallel sides
50
and
52
is 2.22 &mgr;m, while the distance between parallel sides
54
and
5

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