Asymmetric non-volatile memory cell

Details Asymmetric non-volatile memory cell Asymmetric non-volatile memory cell

1995-05-22

1996-04-02

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257322, H01L 29788

Patent

active

055043585

ABSTRACT:
An EPROM memory cell and its fabrication are described. The semiconductor substrate is a first conductivity type. The process begins by forming a conductive gate overlying the substrate, but electrically insulated therefrom by a layer of a first dielectric material. The gate includes a first conductive material, a second layer of dielectric material, and a second conductive layer. A sidewall dielectric spacer is formed adjacent to an edge of the gate. Ions are implanted into the substrate of a species of an opposite conductivity type, at a substantial acute angle relative to a vertical angle with respect to the substrate, with the spacer protecting the substrate from ion implantation adjacent to the gate. Alternatively, the sidewall can be formed subsequent to the second deposition of doping ions at an acute angle.

REFERENCES:
patent: 4771012 (1988-09-01), Yabu et al.
patent: 5073514 (1991-12-01), Ito et al.
patent: 5147811 (1992-09-01), Sakagami
patent: 5158901 (1992-10-01), Kosa et al.
"Optimization of a Source-Side-Injection FAMOS Cell for Flash EPROM Applications" IEDM '91, pp. 315-318, IEEE (1991).
"1/4.mu.m LATID (LArge-Tilted-angle Implanted Drain) Technology" by T. Hori, published in IEDM '89, pp. 777-780.
"Graded-Junction Gate/N-Overlapped LDD MOSFET Structures for High Hot-Carrier Reliability" by U. Okumura et al. Pub. in IEEE Trans on Electron Devices vol. 38, No. 12, Dec. '91 pp. 2647-2656.

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