Asymmetric MOSFET using spacer gate technique

Details Asymmetric MOSFET using spacer gate technique Asymmetric MOSFET using spacer gate technique

1997-09-30

2003-08-12

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S408000

Reexamination Certificate

active

06605845

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to the field of semiconductor devices and, more particularly, to the structure and fabrication of such devices.
2. Description of Related Art
A goal of integrated circuit design is improving device driving capability and device reliability. This goal becomes significantly more complex as device dimensions are reduced, such as for example below channel lengths of 0.5 &mgr;m. Further, increased driving capability or device speed and device reliability are sometimes contradictory goals for traditional metal oxide semiconductor field effect transistor (“MOSFET”) doped region or source/drain architecture, particularly in short channel devices. Conventionally, to improve device performance, the source/drain parasitic resistance of a MOSFET must be minimized. On the other hand, hot electron immunity and better short channel characteristics (e.g., punch-through, drain induced barrier lowering (“DIBL”), threshold voltage roll-off, off-state leakage, etc.) can be significantly improved by adopting source/drain structures that tend to be more resistive. Examples of such structures include structures with implantation characteristics of lightly doped drain (“LDD”), extremely shallow junctions, and wide spacers. Such structures tend to degrade device performance.
As device dimensions are reduced, the lateral electric field generated in MOS devices increases. A strong enough electric field gives rise to so-called “hot-carrier” effects in MOS devices. Hot-carrier effects cause unacceptable performance degradation particularly in MOS devices with short channel lengths, e.g., less than 0.5 microns (&mgr;m). To overcome this problem, lightly doped drains (LDDs) are used to absorb some of the potential into the drain and thus reduce the electric field. The field is reduced by the LDD structure because the voltage drop is shared by the drain and the channel, in contrast to a conventional drain structure, in which almost the entire voltage drop occurs across the channel region. The reduction of the electric field causes a reduction in hot carriers injected into gate oxide which greatly increases the stability of the device.
A LDD structure is typically formed by two implants. The first implant is a lightly doped section self-aligned to the gate electrode. The second implant is self-aligned to sidewall spacers placed adjacent to the gate. The second implant is a heavier dose that forms a low resistivity region of the source and drain region. The second implant is to increase junction depth which lowers both the sheet resistance and the contact resistance of the source and drain and provides better protection against junction spiking.
A major disadvantage of LDD structures is their increased parasitic resistance of the source and drain regions caused by the lightly doped regions of the source/drain. This increase in parasitic channel resistance results in devices that have lower driving current and slower performance.
Examples of short channel effects on device performance are punch-through and DIBL. Punch-through is observed when the electric field in the drain induces a local valley in the energy barrier between source and drain. Such energy forms approximately when the width of the depletion regions around the source and drain meet as a result of the widening of the drain depletion region by a reverse-bias voltage on the drain. This results in an increased current flow from source to drain through the substrate body. DIBL occurs when the application of a drain voltage reduces the barrier height between source and drain at the channel. As a result, the drain voltage creates an increased subthreshold current (i.e., subthreshold current is the current that flows between the drain and source before the magnitude of the gate voltage exceeds the threshold voltage of the device) in the channel region at the silicon-gate oxide interface.
Punch-through and DIBL can be suppressed by keeping the total width of the two depletion regions smaller than the channel length. This is generally accomplished by using shallow junctions and pocket implants, in which an additional implant, such as for example a boron implant, is applied that decreases the lateral widening of the drain-depletion region below the surface without increasing the doping under the junction regions. However, shallow junctions and pocket implants tend to increase parasitic source and drain resistance.
In the conventional fabrication of semiconductor devices, the source and drain regions of a device are fabricated at the same time with the same implantation characteristics (e.g., LDD, shallow junction, pocket implant, etc.). Such fabrication techniques facilitate the processing steps required to make a device, but do not account for the individual performance effects attributable to each of the source region and the drain region individually.
SUMMARY OF THE INVENTION
A field effect transistor and a method for forming a field effect transistor are disclosed. In one embodiment, the field effect transistor includes a semiconductor substrate having a first doped region and a second doped region wherein the first doped region and the second doped region are defined by an implantation property. The implantation property of the first doped region has a first implantation characteristic and the implantation property of the second doped region has a second implantation characteristic, and the first implantation characteristic is different from the second implantation characteristic.


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