Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-07-01
2001-04-24
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S342000, C257S133000, C257S401000
Reexamination Certificate
active
06222232
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a MOS technology power device, particularly a power MOSFET or an Insulated Gate Bipolar Transistor (IGBT).
2. Discussion of the Related Art
Among the most important electric parameters which characterize power MOS devices are the output resistance (R
DSon
), the input capacitance (gate-source capacitance or gate-emitter capacitance) and the feedback capacitance (gate-drain capacitance or gate-collector capacitance).
The output resistance is important during steady-state conditions because the output resistance determines the power dissipation of the power device, and should therefore be as small as possible.
The input and feedback capacitances are instead important during switching because the capacitances determine the turn-on and turn-off time of the power device. Longer turn-on and turn-off times cause a higher power dissipation during switching and limit the operating frequency of the power device.
In order to reduce the input and feedback capacitances, it is necessary to increase the gate oxide thickness and/or to reduce the extension of the area of superposition between the gate electrode, the channel region and the drain layer.
Unfortunately, an increase in gate oxide thickness or reduction in the area of superposition negatively affects the steady-state characteristics of the power device, such as the output resistance. In fact, an increase of the gate oxide thickness would cause an increase of the channel region and accumulation components of the output resistance. A reduction of the distance between the body regions of the elementary cells (or stripes) of the power device in an attempt to reduce the superposition area between the gate electrode and the drain layer would cause an increase of the so-called JFET component of the output resistance.
Conventionally, the distance between the elementary cells or stripes of the power device depends on the lateral diffusion of the body regions and on the requirement that the JFET component of the output resistance is to be kept low. For example, in power devices for low-voltage applications the distance between the elementary cells or stripes of the power device cannot be lower than 5-6 &mgr;m.
In the co-pending European Patent Application No. 95830453.7 filed on Oct. 30, 1995 in the name of the same Applicant, a high-density MOS technology power device is described comprising rectilinear elongated apertures in the insulated gate layer under which rectilinear elongated P type body stripes are formed in an N+ drain layer. The body stripes extend laterally under the insulated gate layer symmetrically with respect to the symmetry axes of the elongated apertures in the insulated gate layer. Inside each body stripe, a plurality of N+ source regions are formed which are disposed in longitudinal succession on opposite sides with respect to a symmetry axis of the body stripe. In this way, it is possible to reduce the distance between adjacent elongated apertures in the insulated gate layer without increasing the JFET component of the output resistance, because the portions of the drain layer positioned between adjacent body stripes experience a current flux from only one side. Device simulations have in fact proved that the output resistance depends on the current density in the portions of the drain layer comprised between adjacent body stripes: an asymmetric current flux allows therefore a reduction of the distance between the body stripes without increasing the output resistance.
However, even in this power device structure the distance between adjacent elongated apertures in the insulated gate layer cannot be reduced significantly because of the symmetrical lateral diffusion of the body stripes under the insulated gate layer.
SUMMARY OF THE INVENTION
According to one aspect, the present invention provides a MOS technology power device structure which allows for the reduction of the input and feedback capacitances without an increase in the output resistance.
According to one embodiment the present invention, a MOS technology power device includes a semiconductor substrate, a semiconductor layer of a first conductivity type superimposed over the semiconductor substrate, an insulated gate layer covering the semiconductor layer, a plurality of substantially rectilinear elongated openings parallel to each other in the insulated gate layer, a respective plurality of elongated body stripes of a second conductivity type formed in the semiconductor layer under the elongated openings, source regions of the first conductivity type included in the body stripes and a metal layer covering the insulated gate layer and contacting the body stripes and the source regions through the elongated openings, characterized in that each body stripe comprises first portions substantially aligned with a first edge of the respective elongated opening and extending under a second edge of the elongated opening to form a channel region, each first portion including a source region extending substantially from a longitudinal axis of symmetry of the respective elongated opening to the second edge of the elongated opening, and second portions, longitudinally intercalated with the first portions, substantially aligned with the second edge of the elongated opening and extending under the first edge of the elongated opening to form a channel region, each second portion including a source region extending substantially from the longitudinal axis of symmetry to the first edge of the elongated opening, the first portions and second portions of the body stripes being respectively aligned in a direction transversal to the longitudinal axis.
In another embodiment of the present invention, the portions of semiconductor layer comprised between adjacent body stripes experience a current flux coming from only one side, and the distance between the body stripes can be reduced without increasing the output resistance of the power device; in addition, due to the fact that the body stripes do not extend symmetrically under the insulated gate layer, the distance between the body stripes can be further reduced.
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Thapar N., et al., “A comparison Of High Frequency Cell Designs For High Voltage DMOSFETs”, Proceedings Of The 6th International Symposium On Power Semiconductor Devices and ICS, ISPSD '94 Proceedings of ISPSD '94 Symposium on Power Semiconductor Devices and IC's, Davos, Switzerland, May 31—Jun. 2, 1994, Konstanz, Germany, Hartung-Gorre Verlag, Germany, pp. 131-135.
Frisina Ferruccio
Magri' Angelo
Zambrano Raffaele
Galanthay Theodore E.
Loke Steven
Morris James H.
Nadav Ori
SGS--Thomson Microelectronics S.r.l.
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