Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2011-05-17
2011-05-17
Vu, Hung (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S283000
Reexamination Certificate
active
07943445
ABSTRACT:
A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.
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Anderson Frederick G.
Collins David S.
Phelps Richard A.
Rassel Robert M.
Zierak Michael J.
International Business Machines - Corporation
Kotulak, Esq. Richard M.
Scully , Scott, Murphy & Presser, P.C.
Vu Hung
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