Asymmetric inside spacer for vertical transistor

Details Asymmetric inside spacer for vertical transistor Asymmetric inside spacer for vertical transistor

2002-06-28

2003-11-04

Ho, Hoai (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000

Reexamination Certificate

active

06642566

ABSTRACT:

TECHNICAL FIELD
The field of the invention is that of DRAM arrays using vertical transistors.
BACKGROUND OF THE INVENTION
It is highly desirable to minimize bitline capacitance (Cbitline) in dynamic random access memories (DRAMs). The magnitude of the voltage stored on the storage capacitor (Vstorage) and signal voltage developed on the bitline conductor (Vsignal) during the data read operation is influenced by the ratio of the storage capacitance to the bitline capacitance. Referring to
FIG. 1
, the signal voltage is given by
Vsignal=0.5*Vstorage*Cstorage/(Cbitline+Cstorage)
where Vstorage is the voltage difference between the stored high and low levels on storage capacitor
405
, and Cbitline is the parasitic capacitance of the bitline including the input capacitance of the sense amplifier. To maximize the signal developed on the bitline, and to maximize the data retention time, the transfer ratio, Cstorage/(Cbitline+Cstorage), must be maximized.
Bitline capacitance slows the switching of the array transistor and reduces the signal developed on the bitline, making sensing (detection of data state) more difficult. A significant portion of the bitline capacitance is due to coupling between the bitline and crossing wordlines. This is particularly true for contemporary DRAM cells employing vertical MOSFETs for the array transistors.
In a well-known prior art array layout shown in plan view in
FIG. 2
, there are two bitline contacts associated with each storage capacitor
400
in the memory array. Deep trench storage capacitors and vertical MOSFETs lie under the intersection of wordlines
430
and bitlines
420
. Contact
425
between bitline and MOSFET is made on each side of a wordline
430
. Significant bitline capacitance is contributed at the points of intersection of a bitline with the orthogonally crossing wordlines. Although this layout has high bitline capacitance, it is particularly immune to variations in bitline to MOSFET contact resistance due to misalignment of the wordline with respect to the location of the vertical MOSFETgate/storage capacitor; while misalignment in one direction reduces the area of one contact, the area of the second contact is unaffected.
In order to reduce the bitline capacitance, an alternate prior art layout which employs a single bitline contact per cell (shown in
FIG. 3
) has been used. Although this design results in significantly reduced bitline capacitance, high resistance between bitline and array MOSFET may result from misalignment of the wordline in a manufacturing process.
FIG. 3
shows misaligned wordlines
430
′, resulting in a rarrower contact
425
′than in teh prior art of FIG.
2
. The differenec is denoted by brackets
426
and
426
′. High resistance between bitline and array MOSFET degrades performance.
In this prior art layout, a single bitline contact to MOSFET is used per cell to reduce bitline capacitance. However, as shown for the case of misaligned wordlines with respect to the vertical MOSFETs/storage capacitors, there may be a reduction in the contact area between bitlines and the transistor. This may lead to failure of the wordline to contact the gate conductor of the vertical MOSFET. The resulting high resistance degrades performance.
The problem is especially acute because of the dual inside spacers employed in the top portion of the storage trench, which are required to avoid exposure of the channel of the vertical MOSFET during the wordline etch process, and to eliminate shorting between the bitline contact and the gate conductor. in
FIG. 5
, two nitride spacers
134
leave only a small amount of poly to make contact between the wordline stack
302
,
304
and gate
205
of the vertical transistor. Such a small amount of material provides a relatively high resistance in the current path of the cell and is susceptible to fluctuations in the manufacturing process. With a small amount of wordline misalignment, as may routinely occur in the manufacturing process, the wordline may fail to connect with the gate conductor. This would render the cell inoperative. A corresponding plan view is shown in
FIG. 4
, in which wordlines
432
are deliberately offset from the capacitor
400
. The result is that bitline contacts
426
have the same dimension as those in FIG.
2
and are insensitive to misaligment.
SUMMARY OF THE INVENTION
The invention relates to a vertical MOSFET DRAM cell containing asymmetric inner spacers.
A feature of the invention is the use of a wordline displaced from the center of the DRAM cell.
Another feature of the invention is the use of the wordline as an etch stop to protect one side of the gate of the vertical MOSFET.
Yet another feature of the invention is the use of a single dielectric protective spacer on the side of the cell opposite the wordline.
Yet another feature of the invention is the provision of a wide gate extension contact between the gate of the vertical MOSFET and the wordline.


REFERENCES:
patent: 6518616 (2003-02-01), Dyer et al.
patent: 6552382 (2003-04-01), Wu

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