Asymmetric field effect transistor structure and method

Details Asymmetric field effect transistor structure and method Asymmetric field effect transistor structure and method

2011-03-29

2011-03-29

Stark, Jarrett J (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S286000, C257S288000, C257SE29255, C257SE21409

Reexamination Certificate

active

07915670

ABSTRACT:
Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).

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Anderson et al., U.S. Appl. No. 11/869,145, Notice of Allowance, Jul. 20, 2010, 4 pages.
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Anderson et al., U.S. Appl. No. 11/869,145, Office Action Communication, Apr. 5, 2010, 14 pages.

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