Asymmetric field-effect transistor having asymmetric channel...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S285000, C257S286000, C257S335000, C257S336000, C257S344000, C257S345000, C257S362000, C257S368000, C257S369000, C257S371000, C257S372000, C257S736000

Reexamination Certificate

active

07968921

ABSTRACT:
An asymmetric insulated-gate field-effect transistor (100) has a source (240) and a drain (242) laterally separated by a channel zone (244) of body material (180) of a semiconductor body. A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. A more heavily doped pocket portion (250) of the body material extends largely along only the source. Each of the source and drain has a main portion (240M or242M) and a more lightly doped lateral extension (240E or242E). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension. These features enable the threshold voltage to be highly stable with operational time.

REFERENCES:
patent: 5113237 (1992-05-01), Stengl
patent: 5780912 (1998-07-01), Burr et al.
patent: 5793090 (1998-08-01), Gardner et al.
patent: 6060745 (2000-05-01), Tadokoro et al.
patent: 6078082 (2000-06-01), Bulucea
patent: 6107149 (2000-08-01), Wu et al.
patent: 6127700 (2000-10-01), Bulucea
patent: 6297114 (2001-10-01), Iwata et al.
patent: 6548842 (2003-04-01), Bulucea et al.
patent: 6566204 (2003-05-01), Wang et al.
patent: 7419863 (2008-09-01), Bulucea
patent: 7642574 (2010-01-01), Bulucea
patent: 7701005 (2010-04-01), Bulucea et al.
patent: 2008/0308878 (2008-12-01), Bulucea
patent: 2008/0311717 (2008-12-01), Bulucea
Brown et al., “Trends in Advanced Process Technology—Submicrometer CMOS Device Design and Process Requirements”,Procs. IEEE, Dec. 1986, pp. 1678-1702.
Buti et al., “Asymmetrical Halo Source GOLD drain (HS-GOLD) Deep Sub-half n-Micron MOSFET Design for Reliability and Performance”,IEDM Tech. Dig., Dec. 3-6, 1989, pp. 26.2.1-26.2.4.
Chai et al., “A Cost-Effective 0.25μm LeffBiCMOS Technology Featuring Graded-Channel CMOS (GCMOS) and a Quasi-Self Aligned (QSA) NPN for RF Wireless Applications”,Procs. 2000 Bipolar/BiCMOS Circs. and Tech. Meeting, Sep. 24-26, 2000, pp. 110-113.
Choi et al., “Design and analysis of a new self-aligned asymmetric structure for deep sub-micrometer MOSFET”,Solid-State Electronics, vol. 45, 2001, pp. 1673-1678.
Hoentschel et al., “Implementation and Optimization of Asymmetric Transistors in Advanced SOI CMOS Technologies for High Performance Microprocessors”, Elec. Devs. Meeting, Dec. 15-17, 2008, pp. 649-652.
Hori et al., “A New MOSFET with Large-Tilt-Angle Implanted Drain (LATID) Structure”,IEEE Elec. Dev. Lett., Jun. 1988, pp. 300-302.
Lamey et al., “Improving Manufacturability of an RF Graded Channel CMOS Process for Wireless Applications”, SPIE Conf. Microelec. Dev. Tech. II, Sep. 1998, pp. 147-155.
Ma et al., “Graded-Channel MOSFET (GCMOSFET) for High Performance, Low Voltage DSP Applications”,IEEE Trans. VLSI Systs. Dig., Dec. 1997, pp. 352-358.
Mikoshiba et al., “Comparison of Drain Structures in n-Channel MOSFET's”,IEEE Trans Elec. Devs., Jan. 1986, pp. 140-144.
Rung et al., “A Retrograde p-Well for Higher Density CMOS”,IEEE Trans. Elec. Devs., Oct. 1981, pp. 1115-1119.
Sanchez et al., “Drain-Engineered Hot-Electron-Resistant Device Structures: A Review”,IEEE Trans. Elec. Devs., Jun. 1989, pp. 1125-1132.
Shima et al., “High RF power transistor with laterally modulation-doped channel and self-aligned silicide in 45nm node CMOS technology”,IEDM Tech. Dig., Dec. 15-17, 2008, pp. 453-456.
Shimizu et al., “High Drivability CMOSFETs with Asymmetrical Source-Drain (ASD) Structure for Low Supply Voltage ULSIs”,Ext'd Abstrs, 21st Conf. Solid State Devs. and Mats., 1989, pp. 125-128.
Su et al., “A High-Performance Scalable Submicron MOSFET for Mixed Analog/Digital Applications”,IEDM Tech. Dig., Dec. 1991, pp. 367-370.
Thompson et al., “MOS Scaling: Transistor Challenges for the 21st Century”,Intel Technology J., Q398, 1998, pp. 1-19.
Tsui et al., “A Versatile Half-Micron Complementary BiCMOS Technology for Microprocessor-Based Smart Power Applications”,IEEE Trans. Elec. Devs., Mar. 1995, pp. 564-570.
Zhao et al., “Improved Analog Hot-Carrier Immunity for CMOS Mixed-Signal Applications with LATID Technology”,IEEE Trans. Elec. Devs., Jun. 1996, pp. 954-957.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Asymmetric field-effect transistor having asymmetric channel... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Asymmetric field-effect transistor having asymmetric channel..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asymmetric field-effect transistor having asymmetric channel... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2650850

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.