Asymmetric dot shape for increasing select-unselect margin...

Static information storage and retrieval – Systems using particular element – Magnetic thin film

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S173000, C365S158000

Reexamination Certificate

active

06798691

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to magnetic memory cells and, more particularly, to a system and method for improving the write selectivity of individual memory cells in a magnetic random access memory (MRAM) array.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
A non-volatile memory circuit maintains stored information even when electricity is removed from the circuit. Recently, advancements in the use of magneto-resistive materials have revolutionized the development of non-volatile memory circuits with the introduction of magnetic random access memory (MRAM). MRAM circuits advantageously exploit the electromagnetic properties of magneto-resistive materials to set and maintain information stored within individual memory cells of the circuit. In particular, MRAM circuits utilize magnetization direction to store information within a memory cell, and differential resistance measurements to read information from the memory cell. In other words, information is stored within an MRAM cell as a magnetic bit, the state of which is indicated by the orientation of magnetization within one layer of the memory cell relative to another layer of the memory cell. In addition, a differential resistance can be obtained from differences in the magnetization directions between layers of the memory cell. Such a differential resistance can be used to read the magnetic state of the bit stored in the MRAM cell.
An MRAM cell typically includes a plurality of layers with at least two magnetic layers separated by a nonmagnetic layer, and therefore, is sometimes referred to as a magnetic stack. A lower magnetic layer (e.g., a pinned magnetic layer) of the magnetic stack is usually fixed in a predefined magnetic direction to be used as a reference direction. To store information, however, the magnetic direction of an upper magnetic layer (e.g., a storage layer or a free magnetic layer), which is separated from the lower magnetic layer by a nonmagnetic layer, can be manipulated into a direction that is parallel or anti-parallel to the magnetic direction of the lower magnetic layer. Note that the term anti-parallel is used herein to describe a magnetic direction that is oriented 180° from the reference magnetic direction of the lower magnetic layer.
In general, a bit of information may be written to an MRAM cell by applying current that induces a magnetic field external to the cell. Such an external magnetic field may then force a majority of the internal magnetic field vectors within the free magnetic layer to align in a direction, either parallel or anti-parallel, relative to the magnetic direction of the pinned magnetic layer. Thus, the magnetic state of the stored bit is determined by the variable magnetic direction within the free magnetic layer. Once the bit is stored, however, the current may be discontinued without losing or altering the magnetic state of the stored bit.
In one example, a bit may be written to the free magnetic layer of an MRAM cell as a logic “0” (i.e., logic low) value when the magnetic direction of the free magnetic layer is substantially parallel to the magnetic direction of the pinned magnetic layer. In another example, a bit may be written to the free magnetic layer of an MRAM cell as a logic “1” (i.e., logic high) value when the magnetic direction of the free magnetic layer is substantially anti-parallel to the magnetic direction of the pinned magnetic layer. In either example, the stored bit may be read from the MRAM cell by measuring the resistance between the free and pinned magnetic layers, such that a logic 1 value is determined by a relatively higher resistance than a logic 0 value.
In addition, an MRAM cell typically includes an easy axis and a hard axis of magnetization, both of which are oriented along a single plane in directions perpendicular to one another. Note that the terms easy axis and hard axis of magnetization are used herein to describe the inherent tendency of the magnetization within the free magnetic layer to align along one axis versus another axis, at times when substantially no external magnetic field is present. In particular, the previously defined parallel or uni-parallel-anti-parallel directions of magnetization are typically oriented along the easy axis of magnetization. Such an orientation along the easy axis usually permits the stored information to be non-volatile. In other words, the magnetization within the free magnetic layer (inc., stored information) may be retained along either the parallel and anti-parallel orientation of the easy axis even when power to the memory cell is removed.
As will be discussed in more detail below, the easy axis of magnetization is usually an inherent result of the shape of the MRAM cell. Thus, the easy axis of magnetization is typically arranged along the length of the MRAM cell, and is sometimes referred to as the long, or longitudinal axis of magnetization. The magnetic state of the MRAM cell is usually defined by the magnetic direction along the easy axis of magnetization. The magnetic hard axis, however, is typically arranged along the width of the MRAM cell, and is sometimes referred to as the short, or transverse axis of magnetization. Since an external magnetic field may be needed to orient the magnetization within the free magnetic layer along the hard axis, the magnetic state of the MRAM cell is not typically stored along the hard axis.
An MRAM circuit typically includes a plurality of bit lines and digit lines, such that the plurality of bit lines is substantially perpendicular to the plurality of digit lines. An MRAM circuit also includes a plurality of MRAM cells, such as those described above, where each of the plurality of MRAM cells is approximately arranged at intersecting regions between individual bit lines and digit lines. In this manner, when current is simultaneously applied along a particular bit line and a particular digit line, the applied current may induce an external magnetic field large enough to switch the magnetization of an individual memory cell. Such an individual memory cell may herein be referred to as a selected memory cell, or the memory cell intentionally targeted for a writing procedure.
During the writing procedure, the multitude of memory cells arranged along the selected bit line and the selected digit line will sense an amount of current typically less than the amount of current sensed by the selected memory cell. Such memory cells are herein referred to as half selected cells, or disturbed cells. Even though less current is applied to these disturbed cells, fabrication process variations may allow a false bit to be unintentionally written to one or more of the disturbed cells. The writing of false bits, however, is undesirable and indicates failure of the memory device to store accurate information. Though all memory cells within an MRAM circuit are generally fabricated at the same time, variations in the fabrication process may produce variations in shape, size, and/or the presence of defects within individual memory cells. It may be these variations within individual memory cells that are typically responsible for the occurrence of false bits.
As such, a particular MRAM cell shape (e.g., an elliptically-shaped memory cell) may store inaccurate information due to its sensitivity to variations in shape, size, and defects. In fact, the variations may be so large that information can be accidentally stored to one or more unselected memory cells (i.e., cells not arranged along the selected bit line or digit line), which exhibit unusually lower switching fields than expected. Sensitivity to variations in shape and size may also disadvantageously reduce the current margin between selected and disturbed cells, thereby reducing the write selectivity between MRAM cells. In other words, the relative difference (i.e., current margin) between the amount of current responsible for switching the magnetization of a disturbed

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Asymmetric dot shape for increasing select-unselect margin... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Asymmetric dot shape for increasing select-unselect margin..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asymmetric dot shape for increasing select-unselect margin... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3258430

All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.