Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2002-07-12
2004-12-28
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000, C326S083000, C326S090000, C327S541000, C327S281000
Reexamination Certificate
active
06836142
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the use of an input/output (I/O) circuit having a digitally controlled impedance to implement an asymmetric bus I/O protocol.
RELATED ART
Modern bus applications are commonly introduced with bus I/O standards tailored specifically to the needs of that application. The bus I/O standards provide specifications to vendors who create products designed to interface with these applications. Each bus I/O standard often has its own specifications for current, voltage, I/O buffering and termination techniques. It would be desirable for programmable logic devices to be compatible with as many bus I/O standards as possible, such that these programmable logic devices are capable of interfacing with as many applications as possible.
FIG. 1
is a block diagram of a conventional high speed digital system
100
, which operates in accordance with a conventional bus I/O standard known as terminated high-speed transistor logic (HSTL) Class I. The HSTL Class I standard provides for a single-ended (asymmetric) termination and unidirectional signal transfer. System
100
includes a first device
101
having an output driver circuit
111
(which is supplied by a V
CCO
voltage equal to 1.5 Volts) and a second device
102
having an input buffer
112
(which operates in response to a reference voltage V
REF
equal to 0.75 Volts and signals generated by first device
101
). The first and second devices
101
and
102
are mounted on a printed circuit board
103
. An electrically conductive trace
104
located on printed circuit board
103
couples output driver
111
of first device
101
to input buffer
112
of second device
102
. In accordance with the HSTL Class I standard, trace
104
has an impedance of 50 ohms. An external dedicated resistor
105
is located on printed circuit board
104
, and connected to the end of trace
104
located adjacent to second device
102
. In accordance with the HSTL Class I standard, resistor
105
is selected to have a matching resistance of 50 ohms, and is biased with a voltage VTT of 0.75 Volts (i.e., V
CCO
/2).
Signals are transmitted in a unidirectional manner from output driver
111
to input buffer
112
via trace
104
. Termination resistor
105
absorbs or prevents signal reflections, which may otherwise interfere with the function of system
100
. Bi-directional communication on trace
104
is prevented or compromised (by slower performance and non-optimal signal integrity) by the presence of immovable fixed resistor
105
. Similarly, bi-directional communication between multiple devices coupled to trace
104
is impossible or impractical in the presence of fixed termination resistor
105
.
Because resistor
105
is fixed on printed circuit board
103
, this resistor
105
cannot be easily removed from system
100
. System
100
is therefore constrained by the presence of resistor
105
, and cannot be easily re-arranged to implement another bus I/O standard (unless that standard requires termination resistor
105
).
It would therefore be desirable to have a programmable logic device that is able to overcome the above-described deficiencies of high-speed digital system
100
.
SUMMARY
Accordingly, the present invention provides a system that replaces one or more dedicated external termination resistors in an asymmetrical bus I/O standard with programmable impedances provided by controlling output driver circuits on integrated circuit chips.
An output driver circuit is used to implement a termination resistor as follows. An I/O circuit according to the present invention includes a pad, an input buffer circuit and an output driver circuit. A first I/O circuit on a first integrated circuit device may be coupled to a second I/O circuit on a second integrated circuit device by a bus line coupled to the pads of the first and second I/O circuits. Instead of being terminated by external dedicated resistors, the bus line is terminated by programmable impedances introduced by the output driver circuits in the first and second I/O circuits.
For example, assume that a signal is being driven from the output driver circuit of the first I/O circuit to the input buffer of the second I/O circuit. In this case, the output driver circuit (or a portion thereof) in the second I/O circuit is used to implement a termination resistor equivalent to termination resistor
105
(FIG.
1
). More specifically, the output driver in the second I/O circuit is tri-stated, such that this output driver is not responsive to signals applied to its input terminal. This output driver circuit includes a plurality of p-channel transistors coupled between the pad and a V
CC
voltage supply terminal, and a plurality of n-channel transistors coupled between the pad and a ground voltage supply terminal. A digitally controlled impedance (DCI) control circuit is used to turn on a particular set of the p-channel transistors and/or the n-channel transistors, thereby providing the desired termination impedance at the second end of the bus line.
Advantageously, signals can also be driven from the output driver circuit of the second I/O circuit to the input buffer of the first I/O circuit. That is, the direction of signal transfer can be reversed. To provide the proper termination, the output driver circuit in the first I/O circuit is used to implement a termination resistor equivalent to termination resistor
105
(FIG.
1
). More specifically, the output driver in the first I/O circuit is tri-stated, and a corresponding DCI control circuit is used to turn on a particular set of the p-channel transistors and/or the n-channel transistors in the output driver, thereby providing the desired termination impedance at the first end of the bus line. Note that the termination resistance previously provided by the output driver circuit of the second I/O circuit is disabled or modified at this time, depending on the particular bus I/O standard being used.
The output driver circuit that is driving the bus line can also be used to provide a desired termination resistance on the driving end of the bus line. This termination resistance can be modeled as a series and/or parallel resistance.
The manner in which the DCI control circuits are used to control the impedances of the output driver circuits is described in commonly-owned U.S. patent application Ser. No. 09/684,539, entitled “Digitally Controlled Impedance for I/O of an Integrated Circuit Driver” filed by David P. Schultz et al, on Oct. 6, 2000. Portions of this case are replicated below to assist in the understanding of the present invention.
The present invention will be more fully understood in view of the following description and drawings.
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Ghia Atul V.
Lesea Austin H.
Hoffman Bernard
Hoffman E. Eric
Tan Vibol
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