Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-02-12
2004-08-31
Phan, Trong (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S318000
Reexamination Certificate
active
06784480
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to integrated circuits and, more particularly, to nonvolatile programmable memory cells.
BACKGROUND OF THE INVENTION
Conventional nonvolatile flash and Electronically Erasable Programmable Read Only Memory (EEPROM) devices are “dual-threshold” Field Effect Transistor (FET) devices. These devices include a floating silicon gate (“floating gate”) isolated from the top programming gate (“control gate”). These devices are programmed (write and/or erase) by applying a set of programming potentials between the control gate and the silicon substrate. Devices are read as being either in the nonconducting state or in the conducting state based on the threshold state of the FET device. Hot carriers, which are usually electrons, are conventionally supplied and injected from the silicon substrate. Electrons are collected by the floating gate to raise the threshold to the nonconducting state for an NFET device and conversely discharged into the substrate to lower the threshold and return to the conducting state. While the reading of the states is similar to the reading of Dynamic Random Access Memory (DRAM) devices, the writing or erasing process typically takes tens or hundreds of milliseconds. Therefore, it is desirable to improve the erase and/or write speed to enhance the range of applications for nonvolatile devices.
The conventional nonvolatile devices discussed above involve high energy (“hot”) charge transport between the substrate and the floating gate. Part of the energy of the hot carriers is transferred to the interface lattice between the silicon substrate and the gate oxide. As a result, interface bonds break and interface characteristics get degraded after multiple write-erase cycles. The term “endurance” relates to these effects that multiple write-erase cycles have on the device. Consequently, the hot charge transport generates surface states at the silicon-oxide interface and creates local weak spots in the gate oxide that negatively affects the device by degrading the FET transconductance (Gm), enhancing the stored charge loss from the floating gate (i.e. retention loss), and reducing the endurance (i.e. operable write-erase cycles) of the device.
It has been proposed to preserve the integrity of the silicon-oxide interface by providing primary charge carrier transport between the floating gate and the control gate. For example, it has been proposed to appropriately design the gate stack such that the charge transport takes place preferentially and primarily between the control gate and the floating gate by field emissions of carriers from either or both the control gate and the floating gate during write and erase operations. The nonvolatile devices include a control gate/floating gate capacitor and a floating gate/substrate capacitor. A programming voltage is capacitively divided between these two capacitors. Therefore, in order to provide the primary charge carrier transport between the floating gate and the control gate, the gate stack is designed so that more of the potential, and thus more of the electric field, is imposed between the control gate and the floating gate rather than between the floating gate and the substrate. Such a device enters a low threshold state by hole transport from the control gate and subsequent collection at the floating gate, or by electron transport from the floating gate through the dielectric layer and discharge to the control gate, or by a combination of both the hole transport and the electron transport as stated above. Conversely, such a device enters a high threshold state by hole transport from the floating gate and subsequent discharge to the control gate, or by electron transport from the control gate through the dielectric layer and collection into the floating gate, or by a combination of both the hole transport and the electron transport as stated above. It is noted that the mechanism for charge transport for such devices is based on field emission alone. Conventional devices operate by multiple mechanisms for charge transport which include hot electron emission from the device channel as well as electron field emission from the substrate for a write operation; whereas for an erase operation, the mechanisms may include avalanche hole emission from the device junction and/or electron field emission from the control gate.
Carrier field emission (or tunneling) is exponentially dependent on the field in the insulator and the potential barrier height for emission into the insulator, as provided by the following equation:
J
E
2
∝
ⅇ
-
(
Φ
B
)
3
2
E
.
For the above equation, J represents current density, E represents the electric field, and &PHgr;
B
represents the barrier height or energy barrier. The carrier transport is capable of being significantly enhanced by increasing the electric field (E) imposed across the insulator and is capable of being significantly reduced by obtaining a larger energy barrier height (&PHgr;
B
) between materials.
Conventional nonvolatile devices may be termed “substrate-sourced-carrier devices” (SSCD) and the non-conventional nonvolatile devices discussed above may be termed “gate-sourced-carrier device” (GSCD). Since the floating gate acts as a capacitive voltage divider, the potential imposed between the control gate and the substrate is divided between the control gate/floating gate capacitor and the floating gate/substrate capacitor. SSCD devices are designed to have higher coupling constant (K>0.5) to achieve a higher potential drop between the floating gate and the substrate to facilitate charge injection from the substrate during a write or erase operation. GSCDs are designed to have lower coupling constants (K<0.5) for a greater potential drop between the control gate and the floating gate for such operation. With the smaller coupling constant, GSCDs are able to have a smaller geometry and are able to provide higher cell and chip density than conventional SSCDs. However, disadvantages with GSCDs include data retention and read disturb problems as explained below.
With respect to the data retention problem, the GSCD is designed to facilitate charge transport between the control gate and the floating gate. The built-in field between the floating gate and the control gate is higher when the charge (electrons or holes) is stored in the floating gate. If the barrier height for carrier emission is sufficiently low, charge is transported more easily between the floating gate and the control gate, resulting in an enhanced stored charge loss, poorer data retention and loss of non-volatility.
With respect to read disturb problems, all bits from the same word line column are subjected to the read-potential between the control gate and the substrate whenever a specific bit is read. The read-potential is positive at the control gate for NFETs. The addition of the read potential to the built-in potential enhances the stored charge loss (electrons to the control gate and holes to the substrate) during the read-pulse period for all those other bits on the word line holding charge in their floating gates. Sufficient charge is capable of being lost due to these read pulses over time to cause permanent loss of data unless the data is periodically refreshed.
The data retention problem and read disturb problem have prevented applications of GSCD in the past. These problems are capable of being designed out of the conventional SSCD by applying an oxide insulator at the floating gate—substrate interface with a high barrier height of 3.2 ev, by applying a thicker oxide-nitride-oxide (ONO) layer on the top and side of the floating gate such that the equivalent oxide thickness (t
ox.eq.
) between the control gate and the floating gate is greater than 70 nm, and by selecting the cell geometry (by enlarging the cell size) to achieve a larger coupling ratio (K>0.5). For GSCD devices, such approaches with K<0.5 require higher write/erase voltages and result in slower write/erase speeds. Any attempt to improve speed by reduc
Micro)n Technology, Inc.
Phan Trong
Schwegman Lundberg Woessner & Kluth P.A.
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