Asymetric data path position and delays technique enabling...

Details Asymetric data path position and delays technique enabling... Asymetric data path position and delays technique enabling...

2008-03-14

2010-11-09

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S189190, C365S230030, C365S230060

Reexamination Certificate

active

07830734

ABSTRACT:
An asymmetric data path position and delays technique enabling high speed access in integrated circuit memory devices which is asymmetric in terms of the delay from the array to the I/O buffers based on the position relative within a known starting address of a pre-fetch field. In accordance with the technique of the present invention, the delay is not only asymmetric in terms of its physical length, but also in the number of pipeline stages and the clocks that control them and can also be asymmetric in terms of the column address required to access each section of the array and its designated pre-fetch field.

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