Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
2002-05-08
2002-10-29
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
Reexamination Certificate
active
06472697
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices having metal conductive lines and particularly to the fabrication of conductive lines that are thicker in critical path areas to improve performance and more particularly to the fabrication of conductive lines and underlying supplemental lines that together are thicker than only the conductive line in critical path areas of the conductive lines.
2) Description of the Prior Art
Wiring delay is a dominant factor in the performance for deep-submicron CMOS devices. With smaller devices, larger wiring delay per unit length is inevitable. In current technology, critical paths are usually made wider to reduce wiring resistance and double pitch is commonly employed. However the double pitch layers cause chip size to increase.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,990,001 (Oda) that shows a process to lower the wiring delays by making the wire lines thicker in critical areas. However, this process is complicated.
U.S. Pat. No.5,960,309 (Takano) shows a method wires devices formed on a semiconductor integrated circuit. The method includes the steps of finding a wiring path between the devices, determining whether or not a delay in transmitting signals through the wiring path is within a predetermined range, and if the delay is out of the constraint, changing the number, or area, or both of them of through-holes of a given via in the wiring path so that the delay meets in the timing constraints. The integrated circuit thus wired is capable of handling signals that require severe delay.
However, these patents can be further improved upon.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a conductive lines that are thicker for critical or major paths wirings.
It is an object of the present invention to provide a method for fabricating a conductive lines that are thicker for critical or major paths wirings by forming supplemental lines under the critical path areas of an overlying conductive lines.
It is another object of the present invention to provide a method for fabricating a conductive lines that are thicker for critical or major paths wirings by forming second supplemental linesunder the critical path areas of an overlying second conductive lines.
To accomplish the above objectives, the present invention provides a method of manufacturing a conductive lines that are thicker for critical or major paths wirings which is characterized as follows. A semiconductor structure is provided having a top surface comprised of a first dielectric layer. Next, we form a plurality (e.g., spaced approximately parallel) of first level conductive lines over the first dielectric layer. The first conductive lines preferably run in a first direction during at least a portion of their length. The first level conductive lines comprised of a first level first conductive line and a first level second conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening.
Then, in a novel step, we form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are preferably about approximately orthogonal to the first level conductive lines. In a key step, we fill the trenches with a conductive material to form supplemental second lines. The supplemental second lines act as additional (or supplemental) thickness for the second level conductive lines hence they are called “supplemental second lines”.
We form second level conductive lines over at least the supplemental second lines and the plug. The second level conductive lines are aligned parallel to the trenches. The trenches formed in critical path areas of the second level conductive lines. The supplemental second lines are not formed to contact the first level conductive lines where a contact is not desired. In the critical path areas of the second level conductive lines, the supplemental second lines underlie the second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance. Furthermore, once the trenches are etched, we can form the supplemental second lines and the second level conductive lines with one metal deposition and one metal etch step. This is a much simpler process.
The present invention to provide a method for fabricating a conductive lines that are thicker for critical or major paths wirings by forming second supplemental lines (e.g.,
38
40
in
FIG. 5A
) under the critical path areas of an overlying second conductive lines.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 5960309 (1999-09-01), Takano
patent: 5990001 (1999-11-01), Oda
patent: 6037649 (2000-03-01), Liou
Cha Randall Cher Liang
Goh Wang Ling
Lim Victor Seng Keong
Lim Yeow Kheng
See Alex
Chartered Semiconductor Manufacturing Ltd.
Hoang Quoc
Nelms David
Pike Rosemary L. S.
Saile George O.
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