Associative memory system with a multi-digit incrementable...

Details Associative memory system with a multi-digit incrementable... Associative memory system with a multi-digit incrementable...

2005-08-30

2005-08-30

Elmore, Reba I. (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S006000, C711S209000, C711S221000

Reexamination Certificate

active

06938145

ABSTRACT:
A computer system includes a central processing unit, an addressable main memory storing data pages and a page table, and an associative memory. The associative memory stores a plurality of entries in accordance with a low order virtual address component issued by the CPU's processor when access to a given page in main memory is sought. Each entry in the associative memory includes fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count. An incrementable multi-digit counter in the CPU stores a current validity count. When access to a data page is sought, a comparator receives: 1) the high order virtual address component of the data page; 2) the high order virtual address component read from the associative memory entry; 3) the multi-digit validity count read from the associative memory entry; and 4) the multi-digit current validity count in the counter. If there is a full match, a switch issues the real page address read from the associative memory entry. If there is not a match, the page table is consulted to obtain the real address of the requested page, and the associative memory is updated accordingly.

REFERENCES:
patent: 5282274 (1994-01-01), Liu
patent: 5628023 (1997-05-01), Bryant et al.

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