Associative cache memory capable of reconfiguring a K-way...

Details Associative cache memory capable of reconfiguring a K-way... Associative cache memory capable of reconfiguring a K-way...

2001-03-07

2001-11-13

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189050, C365S189070, C365S203000, C365S204000, C365S230060, C365S190000, C365S194000

Reexamination Certificate

active

06317351

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to cache memories and, more particularly, to an associative cache memory capable of decreasing power consumption through the reconfiguration of a K-way and N-set cache memory into M-unit, K-way, and N/M-set cache memory.
2. Description of Related Art
The majority of recent microprocessors employ an internal cache memory having a large storage for improving the performance of data access therein. The cache memory has a tag field composed of content addressable memory (CAM) cells and a data field composed of random access memory (RAM) cells. The tag field is accessed for determining whether a required command or data is stored within the current cache memory. This determination is performed whenever the processor fetches the command, or reads out or writes the data, by comparing an address held in itself with an input address. If the two addresses are the same, the cache memory reads out the command or data from the data field, or writes the data in the data field. As such activities with the tag field significantly affect the entire performance of the cache memory, aggressive developments relevant to the tag field in the cache memory have been taken to promote system performance. However, in the case of an embedded system such as a hand-held telephone, decreasing the power consumption is also very important.
FIG. 1
is a block diagram illustrating a general data processing system employing a cache memory, according to the prior art. The system of
FIG. 1
is disclosed in U.S. Pat. No. 5,367,653, entitled “Reconfigurable Multi-Way Associative Cache Memory”.
The data processing system includes a central processing unit (CPU)
100
which controls a main memory
200
, and a multi-way associative cache memory
300
. The main memory
200
and the cache memory
300
are usually a dynamic random access memory (DRAM), and a static random access memory (SAM), respectively. In a processing system, the cache memory
300
of an SRAM has a smaller storage capacity and a higher data access speed than the main memory
200
of a DRAM. Further, the cost per byte of the cache memory
300
is more expensive th an that of the ma in memory
200
. As is known, CPU
100
also includes operational elements for data communications between an arithmetic logic unit (ALU), components of the CPU
100
, and other circuit units.
The data and/or program command (represented as “data” hereinafter) can be stored in the cache memory
300
. The data and an associative tag are stored in the cache memory
300
. The address of the main memory
200
is stored in a main memory address register
110
located in the CPU
100
.
The main memory address held in the main memory register
110
is divided into a few segments. That is, the main memory address includes byte selection address bits ADDR
0
-
1
used as a signal for selecting a single byte of a plurality of main memory bytes stored in the provided cache memory address, and word selection address bits ADDR
2
-
3
used as a signal for selecting a single word from a plurality of main memory words stored in the provided cache memory address. In addition, set select address bits ADDR
4
-
9
are used as a cache address for accessing a set of the cache memory
300
. Tag address bits ADDR
10
-
31
represented as TAG are stored in a tag array of the cache memory
300
. A cache memory controller
120
controls a signal transmission between the CPU
100
and the cache memory
300
. The associative cache memory
300
is composed of tag and data arrays
320
and
340
, respectively.
FIG. 2
is a diagram illustrating the associative cache memory
300
of
FIG. 1
in further detail, according to the prior art. The associative cache memory
300
is a four-way set associative cache memory, including way_
0
302
, way_
1
304
, way_
2
306
, and way_
3
308
. Each way includes sixty-four sets. Since each way has the same circuit structure, only the structure of way_
0
will be described.
The way
0
_
302
is formed of a buffer register
310
, a tag array
320
, a set selection unit
330
, a data array
340
, a set decoder
350
, and a multiplexer
360
.
The buffer register
310
latches the tag address bits ADDR
10
-
31
of the main memory address, provided by way of the cache memory controller
120
. The address will be provided for a bit line signal of the tag array
320
.
The tag array
320
is composed of 64 lines corresponding to SET_
0
through SET_
63
, and each line stores 22 tag bits, respectively. Identical lines of the four ways
302
,
304
,
306
, and
308
construct a single “set”. That is, the first lines of the ways
302
,
304
,
306
and
308
are ‘set_
0
’, the second lines are “set_
1
”, and so forth. Each line arranged in the tag array in a single way is referred to hereinafter
20
as a “set”.
Match lines ML
0
~ML
63
are connected to the sets SET_
0
~SET_
63
of the tag array
320
, respectively. The match line corresponding to the set of the tag array
320
which stores a tag equal to the address bits ADDR
10
-
31
latched in the buffer register
310
is set on a supply voltage level; the remaining match lines are set on a ground voltage level.
The set decoder
350
generates set enable signals SEN
0
through SEN
63
by decoding the set selection address bits ADDR
4
-
9
.
The set selection unit
330
is formed of sixty-four transistors
330
_
0
through
330
_
63
connected between the match lines ML
0
~ML
63
and the word lines DWL
0
~DWL
63
of the data array
340
. The transistors
330
_
0
to
330
_
63
selectively connect the match lines ML
0
~ML
63
with the word lines DWL
0
~DWL
63
, responding to enable signals SEN
0
~SEN
63
provided from the set decoder
350
.
The data array
340
is composed of sixty-four sets as is the tag array
320
. One set is composed of four words WORD
0
through WORD
3
. Sets
340
_
0
through
340
_
63
of the data array
340
are connected to the sets of the tag arrays
320
, through the word lines DWL
0
~DWL
63
, transistors
330
_
0
~
330
_
63
, and the match lines ML
0
~ML
63
, respectively. The data array
340
provides the data, stored in the set associated with the activated word line of the world lines DWL
0
to DWL
63
, to the multiplexer
360
.
The multiplexer
360
selectively outputs one word (out of four words) provided from the data array
340
in response to the word selection address bits ADDR
2
-
3
.
FIG. 3
is a diagram illustrating the tag array
320
of
FIG. 2
in further detail, according to the prior art. The tag array
320
is constructed of a plurality of CAM cells
322
arranged in
64
rows and
22
columns. The word lines WL
0
~WL
63
are arranged horizontally across pairs of bit lines BL
0
/BLB
0
~BL
21
/BLB
21
. The match lines ML
0
~ML
63
are arranged parallel with the word lines WL
0
~WL
63
.
The pairs of bit lines BL
0
/BLB
0
~BL
21
/BLB
21
transfer the tag address bits ADDR
10
-
31
stored in the buffer register
310
and the pair of data bits composed of complementary bits to the CAM cells
322
. The CAM cells
322
store the single-bit data and perform the single-bit comparison (logical exclusive NOR (XNOR)) operation. The CAM cells
322
output the result of the comparison operation to the connected match line. Each of pre-charge transistors
324
_
0
through
324
_
63
is composed of a P-channel metal oxide semiconductor (PMOS) transistor, and includes a current path formed between the supply voltage and an end of the match line MLi(i=0,1, . . . or 63), a gate controlled by a pre-charge signal PRE provided from the cache memory controller
120
.
FIG. 4
is a diagram illustrating the CAM
322
cell of
FIG. 4
in further detail, according to the prior art. Referring to
FIG. 4
, the CAM cell
322
includes a N-channel metal oxide semiconductor (NMOS) transistor
402
, and NMOS transistors
410
through
416
, and a latch
404
. During a pre-charge mode, the pre-charge transistor
324
_
0
through
340
_
63
is turned on in response to the pre-charge signal PRE, and the match line ML is

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