Associating buffers in a bus bridge with corresponding...

Details Associating buffers in a bus bridge with corresponding... Associating buffers in a bus bridge with corresponding...

1998-12-10

2001-11-27

Beausoleil, Robert (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S112000, C711S121000, C711S163000

Reexamination Certificate

active

06324612

ABSTRACT:

BACKGROUND
1. Field of the Present Invention
The present invention generally relates to the field of microprocessor based computers and more particularly to organizing and managing buffers in a bus bridge to improve the performance of a computing system.
2. History of Related Art
Microprocessor based computer systems typically employ a variety of adapters or peripheral devices to provide extended capabilities to the system and to decrease the processing load required of the central processor or processors. As computing systems continue to increase in performance and complexity, the number of peripheral devices has increased commensurately often necessitating the use of multiple layers of peripheral busses to accommodate all of the required peripheral devices and to provide expansion capacity to the system user. Typically, specialized circuits or devices generally referred to as bus bridges provide the functionality required to enable the various busses within a system to communicate information. The increased importance of peripheral devices in modern computers, from the simplest consumer oriented machines to high end enterprise systems, has generated increased attention to the performance of peripheral busses and bus bridges. Increasing the number of instructions a central processor can execute per second results in only a marginal increase in system performance if the system's bus bridges and peripheral busses are operating at their performance limits. Typically, however, the ability to improve bus bridge performance is constrained by compatibility concerns. Accommodating the large base of peripheral devices designed according to a preexisting bus specification limits the ability to make changes to any bus bridge design. Accordingly, improvements to a particular bus bridge design should, to the greatest extent possible, be compatible with existing bus protocols.
Because bus bridges may be coupled between busses operating at different clock frequencies or between a bus that is currently accessible and a bus that is busy, bridges routinely implement a pool of storage buffers for temporarily storing transactions in transit from one bus to another. Each storage buffer is typically configured to store any of a variety of transactions. Some bus bridges, such as bridges compliant with the PCI specification, include the capability to merge or combine transactions. Such capabilities, however, are all too commonly underutilized because the buffer pool organization of conventionally designed bridges coupled with constraints imposed by the bus specifications prevent or significantly diminish the opportunities to take advantage of the combining or merging capabilities of the bridge. Moreover, conventional bridge designs and buffer pool organizations in which transactions are stored in a common pool can unnecessarily hamper performance of commonly invoked procedures such as interrupt handling routines by failing to associate buffered transactions with their sources. Without information concerning the origin of buffered transactions, many common procedures are forced, under the constraints of the relevant bus specification, to account for each transaction in the buffer pool, regardless of whether a given transaction is relevant to the procedure. Accordingly, it is highly desirable to implement a bus bridge designed to take greater advantage of opportunities to combine buffered transactions and improve the efficiency of commonly invoked procedures such as interrupt handling while maintaining compatibility with existing bus specifications and protocols.
SUMMARY OF THE INVENTION
The problems identified above are in large part addressed by a system and bus bridge design in which the bridges buffer pool is organized into multiple buffer sets and configured to associate each buffer set with a corresponding peripheral device. With this organization, the source of buffered transactions can be maintained without requiring tag bits or other information not in compliance with existing bus specifications. The source information can be utilized beneficially to improve the performance and reduce overhead associated with a variety of tasks and routines.
Broadly speaking, a first application of the present invention contemplates a bus bridge including a buffer pool and steering logic. The buffer pool is organized as a plurality of buffer sets including at least a first and second buffer set. The steering logic is adapted to store transactions originating from a first peripheral device to the first buffer set and transactions originating from a second peripheral device to the second buffer set thereby preserving origin information associated with each buffered transaction. In one embodiment, the transactions arrive via a secondary bus, such as a PCI bus, coupled to the bus bridge. The bridge is suitably adapted for combining two or more transactions within each buffer set to produce a single transaction. Each buffer set preferably includes one or more buffers for temporarily storing transactions arriving from the secondary bus and bound for a primary bus that is coupled to the bus bridge through bus interface logic. The primary bus may comprise a host bus connected to one or more processors. Alternatively, the primary bus may comprise an additional PCI bus or other peripheral bus.
The first application of the present invention further contemplates a computer system including at least one processor, a bridge coupled to the processor via a host bus, and a plurality of peripheral devices including first and second peripheral devices coupled to the bridge via a secondary bus. The bridge includes a pool of buffer sets including a first buffer set and a second buffer set. The bridge includes steering logic configured to store transactions into buffer sets associated with the peripheral device corresponding to the transaction such that first device transactions are stored in the first buffer set, second device transactions stored in the second buffer set, and so forth. In one embodiment, the bridge is configured to receive first and second request signals from the first and second peripheral devices respectively. The bridge preferably further includes arbitration logic for arbitrating mastership of the secondary bus in response to the request signals. The bridge is preferably configured to produce at least first and second grant signals for the first and second peripheral devices respectively to indicate mastership of the secondary bus. In this embodiment, the steering logic is suitably configured to receive the first and second grant signals and to determine therefrom the source of a subsequent transaction.
The first application of the present invention still further contemplates a method of buffering transactions in a bus bridge according to the source of the transaction. A first transaction is received and a first peripheral device identified as its source. Upon identifying the first peripheral device as the source of the first transaction, a first buffer set is selected and the first transaction stored in the first buffer set such that the source of the first transaction is indicated by the presence of the first transaction within the first buffer set. Similarly, a second transaction from a second peripheral device is received and its source identified. A second buffer set is then selected and the second transaction stored in the second buffer set. In an embodiment emphasizing the combining of transactions, additional transactions are received and stored in the appropriate buffer sets. Combining of transactions within a buffer set may then proceed without affecting the contents of the remaining buffer sets. In this manner, a third transaction received from the first peripheral device could be stored in the first buffer set and combined, if appropriate, with the first transaction without regard to transactions in other buffer sets, such as the second transaction, in the second buffer set. Combining occurs when multiple sequential memory write transactions are combined into a single bus transaction. I/O p

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