Assisted trace facility to improve CPU cache performance

Details Assisted trace facility to improve CPU cache performance Assisted trace facility to improve CPU cache performance

2006-09-08

2008-12-30

Nguyen, Hiep T (Department: 2187)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

Reexamination Certificate

active

07472218

ABSTRACT:
A system and method for recording trace data while conserving cache resources includes generating trace data and creating a cache line containing the trace data. The cache line is assigned a tag which corresponds to an intermediate address designated for processing the trace data. The cache line also contains embedded therein an actual address in memory for storing the trace data, which may include either a real address or a virtual address. The cache line may be received at the intermediate address and parsed to read the actual address. The trace data may then be written to a location in memory corresponding to the actual address. By routing trace data through a designated intermediate address, CPU cache may be conserved for other more important or more frequently accessed data.

REFERENCES:
patent: 6002875 (1999-12-01), Stolberg
patent: 7305590 (2007-12-01), Miyamoto
patent: 2006/0112310 (2006-05-01), McHale et al.

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