Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-03-25
2001-04-24
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S026000, C326S027000, C326S017000, C326S087000, C326S030000
Reexamination Certificate
active
06222389
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of bus drivers, and in particular, to a Thevenized assisted gunning transceiver logic (AGTL) bus driver to avoid 1.5 volt power supply requirements.
2. Background Information
Digital computer systems and the like often include a plurality of integrated circuits (IC's), for example, VLSI (very large scale integration) circuits, which are interconnected for conducting digital communications by transmission lines. Drivers (transmitters) and receivers are provided to interface the VLSI components of such systems to the transmission lines. A combined transmitter (driver) and receiver circuit is called a transceiver.
The transmission lines are conventionally traces which are formed on a suitable substrate, such as a PCB (printer circuit board). For example, so-called microstrip traces and strip line traces can be employed to form transmission lines having characteristics impedances on the order of about 50 ohms to 70 ohms. In keeping with standard practices, such transmission lines have their opposite ends terminated in their characteristic impedance (50 to 70 ohms). Thus, the output load on a driver for such a transmission line may be as low as 25 ohms to 35 ohms. or so, i.e., the effective resistance of the parallel resistive terminations of 50 to 70 ohms at each end of the transmission line (disregarding other loads on the bus).
CMOS technology is attractive for fabricating VLSI circuits having relatively high gate densities, but the nominal rail-to-rail voltage swing (nominally, 0 to 5 volts) of standard CMOS circuits tends to cause the output drivers for such circuits to dissipate excessive amounts of power internally whenever the drivers are working into low impedance loads, such as terminated transmission lines of the above-described type. The need for relatively low power drivers and for compatible receivers which could be economically and reliably implemented in existing CMOS technology for interfacing VLSI CMOS circuits to relatively low impedance terminated transmission lines was addressed by William F. Gunning with his so-called “Gunning Transceiver Logic” or GTL.
Gunning transceiver logic (GTL) and bus design are disclosed in U.S. Pat. No. 5,023,488, which issued Jun. 11, 1991, which can be consulted for additional background information. Briefly, the Gunning patent describes very wide channel, open drain, N-channel CMOS (complementary metal oxide semiconductor) drivers and cascade CMOS receivers for interfacing VLSI (very large scale integrated) CMOS circuits to transmission lines, which are terminated by their characteristic resistive impedances, to voltage levels on the order of about 1.2 volts-2.0 volts. These GTL (Gunning Transceiver Logic) drivers and receivers typically operate with a voltage swing on the order of about 0.8 volts-1.4 volts on such transmission lines for carrying out binary communications between CMOS circuits configured to operate with standard 5 volts rail-to-rail voltage swings for their internal signals.
In a practical implementation, the GTL bus can take the form of a transmission line on a circuit board (bus and transmission line may be used interchangeably herein). The GTL bus/transmission line is generally terminated at both ends with a pull-up resistor to the VDD voltage which is usually 1.2 to 1.5 volts. The bus terminating resistors are generally 70 to 100 ohm resistors, therefore, the effective driver load may be as low as 35 ohms (not considering the device loads that may be present). In the field of transmission lines, to reduce problems with signal reflections, for example, it is well known that the signal lines should be terminated with resistors having a resistance value equal to the characteristic impedance of the bus.
By definition, the characteristic impedance of a transmission line is the ratio of the voltage and current at any point on the line, for an infinitely long line, i.e., a line with no reflected waves. The characteristic impedance of a particular line at a particular frequency is dependent on its physical properties, e.g., the inherent resistance, conductance, capacitance and inductance per unit length of the conductors and insulators, and on its design, e.g., the spacing between the conductors. According to transmission line theory, when a line is resistively terminated with its characteristic impedance, there are no reflected waves, and maximum power transfer can take place. However, depending on the length of the line/bus, the capacitive loads due to devices on the line/bus, etc., the characteristic impedance of the line/bus is affected. The result of an overloading the bus is that less than optimal power transfer can be achieved, and signal degradation will result. To deal with this problem, assisted Gunning transceiver logic was developed.
Assisted Gunning transceiver logic (AGTL) differs from conventional Gunning transceiver logic (GTL) in that the AGTL driver “assists” the bus terminators in pulling the bus up to the specified voltage. That is, when a particular driver gets control of the bus and puts a “1” on the bus, the driver actively drives the bus to 1.5 volts (the same voltage as the terminators are tied to) with approximately the characteristic impedance, e.g., 40 ohms. This assists in pulling up the bus to the specified voltage, as well as providing a local termination on the bus stub that the driver is on, thereby damping overshoot.
As computer performance demands increase, new, higher speed logic with increased density is developed to fulfill these needs. To reduce overall power dissipation, modern microprocessors and associated circuits are being designed with lower voltage implementations, which in turn, requires power supplies to provide lower voltages with higher current capacities.
For example, Pentium® II Xeon™ processors have unique requirements for voltages supplied to them. Their bus implementation in particular, called the “assisted gunning transceiver logic +” (AGTL+) bus, requires a particular voltage level (1.5 volts).
The AGTL bus type is planned to have a prominent role in future Intel® products. For example, AGTL is also currently the interface used as the Intel® Merced™ processor bus. The Merced™ processor is a 64-bit processor and the first in the Intel® IA-64™ product family. This processor incorporates performance enhancing processing architecture techniques, such as explicit parallelism, predication and speculation. In explicit parallelism, at compile time, parallelism opportunities are identified in the software which allows for an optimal structuring of machine code to deliver maximum instruction level parallelism before execution, significantly enhancing processor utilization.
Briefly, predication relates to branch prediction, and in particular, to avoiding a wrong branch prediction which results in the purge of an instruction pipeline. In predication, branch paths are assigned special flags called predicate registers, e.g., “p1” for a “then” path, and “p2” for an “else” path. At run time, a compare statement stores a true or false value in the predicate registers. Both paths are then executed by the processor, however, only results from the path with a true predicate flag are used. Branches, and the possibility of associated mispredicts, are removed, the pipeline remains full, and performance is increased. Studies suggest that predication can reduce the number of branches by more than 50% and reduce the number of mispredicts by as much as 40%.
Speculation is directed at overcoming memory latency. Traditional architectures allow memory loads to be scheduled before the data is needed to reduce memory latency, that is, the processor time wasted while slower memory provides data needed by the faster processor. However, branches and other exceptions in instruction flow are a barrier to this pre-loading of data from memory. In speculation, memory loads are speculatively scheduled even in instruction streams with branches. If an exception occurs, this event is stored and a “chec
International Business Machines - Corporation
Lynt Christopher H.
Tan Vibol
Tokar Michael
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