Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-05-12
2008-09-02
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07421678
ABSTRACT:
One embodiment of the present invention provides a system that determines an assist feature placement. During operation, the system receives an initial assist feature placement for a layout. Next, the system determines assist feature perturbations using the initial assist feature placement. An assist feature perturbation typically comprises a few simple polygons. The system then determines perturbation values at evaluation points in the layout using the assist feature perturbations and an analytical model. If a process-sensitivity model is used, the perturbation value at an evaluation point is associated with the change in the through-process window at that point in the layout. Next, the system determines a change in the value of an objective function using the perturbation values. The objective function can be indicative of the overall manufacturability of the layout. The system then determines an assist feature placement using the change in the value of the objective function. For example, the system can determine an assist feature placement using an assist feature perturbation which minimizes the objective function value.
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patent: 7315999 (2008-01-01), Melvin et al.
patent: 2007/0168898 (2007-07-01), Gupta et al.
Schellenberg et al., Adoption of OPC and the impact on design and layout, Jun. 2001, ACM/IEEE, pp. 89-92.
Gupta et al., Detailed Placement for Improved Depth of Focus and CD Control, Jan. 2005, ACM/IEEE pp. 343-348.
Barnes Levi D.
Melvin, III Lawrence S.
Painter Benjamin D.
Chiang Jack
Doan Nghia M
Park Vaughan & Fleming LLP
Synopsys Inc.
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