Electrical computers and digital data processing systems: input/ – Interrupt processing – Programmable interrupt processing
Reexamination Certificate
2007-05-29
2007-05-29
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
Programmable interrupt processing
C710S268000
Reexamination Certificate
active
10935771
ABSTRACT:
Techniques and mechanisms provide management of interrupt requests in a system, such as a programmable chip system. The system may include multiple master components and slave components. Techniques and mechanisms are described for assigning interrupts to slave components on a per master component basis. When a slave component initiates an interrupt request, a master component associated with the request will handle the interrupt without disrupting operation of other master components in the system.
REFERENCES:
patent: 4495569 (1985-01-01), Kagawa
patent: 4930070 (1990-05-01), Yonekura et al.
patent: 5125093 (1992-06-01), McFarland
patent: 6483342 (2002-11-01), Britton et al.
patent: 6738847 (2004-05-01), Beale et al.
patent: 6952749 (2005-10-01), Kim
patent: 6996796 (2006-02-01), Sanchez et al.
patent: 7076595 (2006-07-01), Dao et al.
A Comparison of Five Different Multiprocessor Soc Bus Architectures, Ryu et al., IEEE, 2001.
A Field Programmable System Chip with Combines FPGA and ASIC Circuitry, Andrew et al., IEEE, 1999.
Bus Architecture of a System on a Chip with User-Configurable System Logic, Winegarden, IEEE, 2000.
AMBA Embedded Controller Platform with Multimaster AMBA, Alliance Core, Oct. 18, 2002.
Overview of Exacalibur, Leon, Microblaze, Nios OpenRisc, and Virtex II Pro, Driessens et al., 2003.
Altera Corporation, 70 page document entitled, “Excalibur, Nios Tutorial”, Document Version 1.1, Document date Apr. 2002, Copyright 2002, http://www.altera.com/literature/tt/tt—nios—hw—apex—20k200e.pdf.
Altera Corporation, 14 page document entitled, “Quartus II Handbook, vol. 1, 2. System Design Using SOPC Builder”, Dec. 2004, qii51003-2.1, http://www.altera.com/literature/hb/qts/qts—qii51003.pdf.
Altera Corporation, 14 page document entitled, “Quartus II Handbook, vol. 4, 2. Tour of the SOPC Builder User Interface”, Feb. 2005 QII54002-1.0, http://www.altera.com/literature/hb/qts/qts—qii54002.pdf.
Xilinix Development System, 32 page document entitled, “MicroBlaze Development Kit Tutorial”, Copyright 1994-2002, http://www.ee.calpoly.edu/cpe-329/EDK—Resources/mb—tutorial—c2bits.pdf.
Allen Timothy
Fairman Michael
Altera Corporation
Beyer & Weaver, LLP
Dang Khanh
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