Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-03-06
2007-03-06
Lin, Sun James (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10893472
ABSTRACT:
A method and apparatus provides a mechanism to transform or “morph” Formal verification method assertions so that an assertion defined in one Design Under Test (DUT) can be replicated, or derived, to propagate into other related DUTs. Using the method and apparatus of the present invention, individual DUTs can better leverage assertions defined independently in other DUT environments. This, in turn, provides for greater productivity and a faster, smoother verification process-using Formal and Assertion Based Verification methods.
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Chang Si-En
Qiu Xiaogang
Gunnison McKay & Hodgson, L.L.P.
Lin Sun James
Mckay Philip J.
Sun Microsystems Inc.
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