Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-09-21
2009-10-13
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07603636
ABSTRACT:
An assertion generating system is disclosed. In an assertion generating system207, a graphical editor201generates design data of a semiconductor integrated circuit by graphically editing a specification (finite state machine, process sequence) of the semiconductor integrated circuit with the use of a state transition table and a state transition figure or by editing the process sequence into a timing chart and a time series figure based on user operations, and a syntax analyzer203and a property extractor204generate a property that verifies the specification of the semiconductor integrated circuit based on the design data. The assertion generator205converts the property into an assertion description language206.
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Dickstein & Shapiro LLP
Ricoh & Company, Ltd.
Siek Vuthe
LandOfFree
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