Assertion description conversion device, method and computer...

Details Assertion description conversion device, method and computer... Assertion description conversion device, method and computer...

2007-08-21

2009-11-10

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07617469

ABSTRACT:
An assertion description conversion device comprising: verification target identification unit parsing the syntax of a high-level assertion description described by a high-level assertion description language for verification of an inputted design description of a broader term to identify a verification target; design description searching unit searching a description on the verification target in a design description of a broader term; verification target description conversion unit converting the description of the verification target into a design description of a narrower term according to the design description of the narrower term corresponding to the description searched by the design description searching unit; verification content analysis unit for analyzing verification contents for the verification target described in the high-level assertion description; and verification content description conversion unit for converting the verification contents analyzed by the verification content analysis unit into the description format of a low-level assertion description language for verification of a design description of the narrower term.

REFERENCES:
patent: 6510541 (2003-01-01), Fujiwara et al.
patent: 7363610 (2008-04-01), Alfieri
patent: 7409670 (2008-08-01), Pritchard et al.
patent: 2004/0025127 (2004-02-01), Takenaka
patent: 2005/0144581 (2005-06-01), Imai
patent: 2007/0250303 (2007-10-01), Imai et al.
Gajski et al, High-Level Synthesis, Introduction to Chip and System Design, Chapter 7.

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