Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-03-09
2004-09-21
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
With measuring or testing
C438S109000, C438S119000
Reexamination Certificate
active
06794202
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to assembling microelectronic assemblies and more specifically relates to methods for temporarily connecting microelectronic elements together for testing before the elements are permanently attached to one another.
BACKGROUND OF THE INVENTION
Modern electronic devices utilize semiconductor chips, commonly referred to as “integrated circuits” which incorporate numerous electronic elements. These chips are mounted on substrates that physically support the chips and electrically interconnect each chip with other elements of the circuit. The substrate may be a part of a chip package including a single chip and equipped with terminals for interconnecting the chip with external circuit elements. The interconnection between the chip and its supporting substrate is commonly referred to as a “first level” interconnection. The interconnection between the substrate and the larger elements of the circuit is commonly referred to as a “second level” interconnection.
In a wire bonding process, the substrate has a top surface with a plurality of electrically conductive contact pads disposed on the top surface in a ring-like pattern. The chip is secured to the top surface of the substrate, at the center of the ring-like pattern, so that the chip is surrounded by the contact pads on the substrate. The chip is mounted in a face-up disposition, with the back surface of the chip confronting the top surface of the substrate and with the front surface of the chip facing upwardly, away from the substrate, so that electrical contacts on the front surface are exposed. Fine wires are connected between the contacts on the front face of the chip and the contact pads on the top surface of the substrate. These wires extend outwardly from the chip to the surrounding contact pads on the substrate. In wire-bonded assemblies, the area of the substrate occupied by the chip, the wires and the contact pads are substantially greater than the surface area of the chip itself.
In order to save valuable space on the top surface of substrates, certain microelectronic assemblies use a die attach method commonly referred to as “flip chip” bonding. In flip-chip bonding, contacts on the front surface of the chip are provided with bump leads such as balls of solder protruding from the front surface of the chip. The chip is designed for being connected with a substrate having contact pads arranged in an array corresponding to the array of contacts on the chip. The chip is inverted so that its front surface faces toward the top surface of the substrate, with each contact and solder bump on the chip being aligned with a corresponding contact pad of the substrate. The assembly is then heated to melt the solder so as to bond each contact on the chip to a corresponding contact pad of the substrate. Flip-chip bonding is well suited for use with chips having a large number of input/output (“I/O”) contacts. However, assemblies made by flip-chip bonding are quite susceptible to thermal stresses because the solder interconnections are relatively inflexible, and may be subjected to very high stress upon differential expansion of the chip and substrate. These difficulties are particularly pronounced with relatively large chips. Moreover, it is difficult to test a chip having an area array of contacts before attaching the chip to the substrate.
U.S. Pat. Nos. 5,148,265 and 5,148,266, the disclosures of which are hereby incorporated by reference herein, describe, in certain preferred embodiments, microelectronic packages having a set of pads in the form of terminals that may be mounted on a dielectric layer such as a flexible sheet. The terminals may be connected to contacts on the chip by flexible leads and may be supported above the surface of the chip by a compliant layer such as an elastomer provided between the terminals and the chip, typically between the dielectric layer and the chip. Masses of solder may be provided on the terminals for connecting the assembly to an external circuit element such as a circuit board or other substrate having corresponding contact pads.
The electrical interconnections between the conductive terminals of the chip package and the external circuit element are typically made by using fusible conductive elements, such as solder balls. The solder balls are positioned between the conductive terminals on the chip package and the contact pads on the external circuit element and then reflowed by raising the temperature of the solder balls above a predetermined temperature, generally referred to as the melting point of the solder balls. The melting point is defined as the temperature at which the solder balls transform from a first solid or frozen condition to a second molten or at least partially liquid condition. Once the solder balls have transformed to the second at least partially liquid condition, the solder balls remain in that condition as long as the temperature is maintained at or above the melting point. As described, for example, in Multi-Chip Module Technologies And Alternatives: The Basics, Doane and Franzon, Editors (1993), pp. 468-471, surface tension in the molten solder tends to urge each solder mass into a generally barrel-shaped object having neck portions at the junctures between the solder masses and the contact pads on the opposing microelectronic elements. After the conductive terminals of the chip package and the contact pads of the external circuit element have been electrically interconnected by the reflowed solder balls, the temperature of the solder balls may be reduced to a level below the melting point, whereupon the solder balls transform from the second at least partially liquid condition to the first solid condition. The refrozen solder balls both mechanically and electrically interconnect the chip contacts with the contact pads on the external circuit element.
Methods for electrically connecting contacts of one microelectronic element to the conductive features of another microelectronic element are disclosed in certain embodiments of U.S. Pat. No. 5,518,964, the disclosure of which is hereby incorporated by reference herein. In certain embodiments of U.S. Pat. No. 5,518,964, a component has individual chip regions. A wafer, having a number of semiconductor chips, is assembled with the component so that each chip is connected to a chip region. Features of the chips are bonded to features of the chip regions. In certain embodiments, conductive features of the component receive an electrically conductive bonding material that is applied in spots on the conductive features. The spots of electrically conductive bonding material are applied by coating a resist layer over the conductive features and photolithographically patterning the resist to form openings in the resist at the desired locations for the spots of bonding material. The electrically conductive bonding material is applied in each opening in the resist by electroplating. The conductive features are joined with contacts of the semiconductor chips in certain embodiments, using the spots of bonding material.
U.S. Pat. No. 4,875,617 discloses a method of providing gold-tin eutectic bumps on an integrated circuit wafer or on the tape or other substrate carrier. The quantity of tin reacting with gold in the method is limited and controlled, allowing gold consumption to be reduced by an order of magnitude. A first layer of gold is provided on bonding pads of the wafer after formation of the integrated circuits and a layer of tin is formed on the first gold layer. The first gold and tin layers are then thermally treated at a temperature above 280° C. to form gold-tin eutectic bumps on the first gold layer. A second gold layer is then provided as spots on a tape or other substrate carrier. The second gold layer has a thickness of about 5 percent of the gold rich eutectic body. After dicing the wafer into individual integrated circuit chips, the eutectic body on the chip's pads is placed on and bonded to the second gold layer by heating to a temperature greater than the
Beroz Masud
Light David
Coleman W. David
Lerner David Littenberg Krumholz & Mentlik LLP
Tessera Inc.
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