Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-01-31
2008-09-16
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07426708
ABSTRACT:
A relatively small amount of programmable or reprogrammable logic (pro-Logic) is included in a mostly-ASIC device so that such re/programmable logic can be used as a substitute for, or for bypassing a fault-infected ASIC block (if any) either permanently or at times when the fault-infected ASIC block is about to perform a fault-infected operation (bug-infected operation). The substitution or bypass does not have to be a permanent one that is in effect at all times for the entirety of the fault-infected ASIC block. Instead affected outputs of the faulty ASIC block can be disabled from working just at the time they would otherwise initiate or propagate an error. Such fault-infected operations of the temporarily deactivated ASIC block(s) may be substituted for by appropriately programmed pro-Logic at the appropriate times. Thus, a fault-infected ASIC block that is 99% good (for example) and operates improperly just 1% of the time can continue to be gainfully used for that 99% of the time when its operations are fault free and can be blocked from having its erroneous output(s) used only in the 1% time periods (example) when its behavior is faulty. During those faulty times, a relatively small amount of the pro-Logic can be used as a fault-correcting or fault-bypassing substitute for the fault-infected ASIC block. This substitution or bypassing can be activated after initial design of the mostly-ASIC circuitry and/or after pilot production and/or mass production thereby providing for cost saving and faster time to market and/or for repair or maintenance even years after installation and use of the mostly-ASIC device.
REFERENCES:
patent: 5655069 (1997-08-01), Ogawara et al.
patent: 5852561 (1998-12-01), Chan et al.
patent: 6178541 (2001-01-01), Joly et al.
patent: 6334207 (2001-12-01), Joly et al.
patent: 6539052 (2003-03-01), Hessel et al.
patent: 6608589 (2003-08-01), Devereux et al.
patent: 6618839 (2003-09-01), Beardslee et al.
patent: 6744274 (2004-06-01), Arnold et al.
patent: 6766406 (2004-07-01), Gasperini et al.
patent: 6769107 (2004-07-01), Watkins
patent: 6937493 (2005-08-01), Krause et al.
patent: 7024641 (2006-04-01), Watkins
patent: 7042899 (2006-05-01), Vaida et al.
patent: 2002/0066956 (2002-06-01), Taguchi
patent: 2002/0173298 (2002-11-01), Elayda et al.
patent: 2003/0014743 (2003-01-01), Cooke et al.
patent: 2003/0052176 (2003-03-01), Nozawa et al.
patent: 2003/0099358 (2003-05-01), Michael et al.
patent: 2004/0034843 (2004-02-01), Osann, Jr.
patent: 2004/0183564 (2004-09-01), Schadt et al.
patent: 2006/0101288 (2006-05-01), Smeets et al.
patent: 2006/0117274 (2006-06-01), Tseng et al.
patent: 2006/0179435 (2006-08-01), Hirase
patent: 2006/0225002 (2006-10-01), Hassoun et al.
patent: 2006/0248493 (2006-11-01), Osann, Jr.
Zuchowski, Paul S.; A Hybrid ASIC and FPGA Architecture; 2002; IEEE; pp. 187-194.
International Search Report, PCT/US06/02858, mailing date May 29, 2008.
Written Opinion of the International Searching Authority, PCT/US06/02858, mailing date May 29, 2008.
Chiang Jack
MacPherson Kwok & Chen & Heid LLP
Memula Suresh
Nanotech Corporation
LandOfFree
ASICs having programmable bypass of design faults does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with ASICs having programmable bypass of design faults, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and ASICs having programmable bypass of design faults will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3991429