ASIC having flexible host CPU interface for ASIC adaptable for m

Details ASIC having flexible host CPU interface for ASIC adaptable for m ASIC having flexible host CPU interface for ASIC adaptable for m

1997-05-06

1999-06-29

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710126, 710131, 710129, G06F 1340

Patent

active

059163127

ABSTRACT:
A CPU interface having an 8-bit mode in which the interface is capable of interfacing with a host CPU having 8-bit data bus, and a 16-bit mode in which the interface is capable of interfacing with a host CPU having a 16-bit data bus. The host CPU interface is further capable of switching between its 8-bit and 16-bit modes in real time in response to a 16-bit host CPU entering sections of 8-bit or 16-bit software. The interface also has "direct" and "indirect" addressing modes, so that the interface can send or receive time-multiplexed data, and receive address information on a single bus ("indirect" mode) or send or receive data, and receive address information in parallel on separate buses ("direct" mode).

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patent: 5761478 (1998-06-01), Chen et al.
patent: 5781746 (1998-07-01), Fleck

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