Article comprising an oxide layer on a GaAs or GaN-based...

Details Article comprising an oxide layer on a GaAs or GaN-based... Article comprising an oxide layer on a GaAs or GaN-based...

1998-11-12

2002-10-22

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S411000, C257S289000

Reexamination Certificate

active

06469357

ABSTRACT:

TECHNICAL FIELD
This invention pertains to articles that comprise an oxide layer on a GaAs-based or GaN-based semiconductor body, e.g., a field effect transistor (FET).
BACKGROUND OF THE INVENTION
GaAs-based transistors and circuits are widely used in, for instance, wireless communication apparatus, due inter alia to the relatively high electron mobility in GaAs, the availability of semi-insulating GaAs substrates, and the relative simplicity of manufacturing processes.
Much effort has been directed towards GaAs-based MOS-FETs. See, for instance, T. Mimura et al.,
IEEE Transactions on Electron Devices
, Vol. ED-27(6), p. 1147 (June 1980) for a review of early work. The authors of that paper concluded (p. 1154) that, although the main features of the results achieved so far are promising, “. . . some technological problems remain, including anomalous behavior of the dc and low-frequency operation of the devices. Undoubtedly, these problems are associated with the high density of surface states involved in the GaAs MOS system.” See also A. Colquhoun et al.,
IEEE Transactions on Electron Devices
, Vol. ED 25(3), p. 375 (March 1978), and H. Takagi et al.,
IEEE Transactions on Electron Devices
, Vol. ED 25 (5), p. 551 (May 1978). The former discloses a device that comprises an etched notch that defines the channel thickness. Such a non-planar structure would be relatively difficult to make repeatably, and thus is less desirable than a planar MOS-FET would be.
As pointed out by Mimura et al., the early devices suffered from poor gate oxide/GaAs interface quality, including a high density of interface states. In recent years, substantial effort has been directed at this problem.
For instance, U.S. Pat. No. 5,451,548 discloses formation of a Ga
2
O
3
film on GaAs by e-beam evaporation from a high purity single crystal of Gd
3
Ga
5
O
12
. See also U.S. Pat. No. 5,550,089, and U.S. Patent application Ser. No. 08/408,678, incorporated herein by reference, which disclose GaAs/Ga
2
O
3
structures with midgap interface state density below 10
11
cm
−2
eV
−1
. See also M. Passlack et al.,
Applied Physics Letters
, Vol. 69(3), p. 302 (Jul. 1996) which reports on the thermodynamic and photochemical stability of low interface state density GaAs/Ga
2
O
3
/SiO
2
structures that were fabricated using in situ molecular beam epitaxy. Other pertinent publications are M. Passlack et al.,
Applied Physics Letters
, Vol. 68(8), p. 1099 (Feb. 1996); and M. Hong et al.,
J. of Vacuum Science and Technology B
, Vol. 14(3), p. 2297, (May/June 1996).
The parent of this continuation-in-part application discloses GaAs-based semiconductor bodies with an oxide layer thereon, the oxide having overall composition Ga
x
A
y
O
z
, where Ga is substantially in a 3+oxidation state, A is one or more electropositive stabilizer element adapted for stabilizing Ga in the 3+oxidation state, x is greater than or equal to zero, z is selected to satisfy the requirement that both Ga and A are substantially fully oxidized, and y/(x+y) is greater than 0.1. Thus, in one embodiment x=0, and A is Gd, the oxide being Gd
2
O
3
.
U.S. patent applications Ser. No. 09/122,558, filed Jul. 24, 1998 by Chen et al., and Ser. No. 09/156719, filed Sep. 18, 1998 by Hong et al., disclose methods of making GaAs-based MOS-FETs having gate oxide of composition Ga
x
A
y
O
z
, as described above.
A MOS structure basically is a planar capacitor, with the capacitance depending linearly on the dielectric constant of the oxide, and inversely on the thickness of the oxide layer. In order to obtain GaAs-based MOS structures with increased capacitance per unit area, it would be desirable to have available structures with oxide layer thickness less than previously required to give acceptably low leakage current. This application discloses such GaAs-based MOS structures.
All patents, patent applications, and scientific papers that are cited herein are incorporated into this patent application by reference.
SUMMARY OF THE INVENTION
As will be described in more detail below, the parent of this continuation-in-part application discloses articles comprising a novel dielectric layer on GaAs-based semiconductors, and a method of making the article.
More specifically, the article comprises an oxide layer on a GaAs-based semiconductor body, and forming an interface therewith. The article further comprises a metal contact disposed on each of the oxide layer and the semiconductor body. Associated with the interface is a midgap interface state density of at most 1×10
11
cm
−2
eV
−1
at 20° C.
Significantly, the oxide layer has overall composition Ga
x
A
y
O
z
, where Ga substantially is in a 3+ oxidation state, where A is one or more electropositive stabilizer element for stabilizing Ga in the 3+ oxidation state, x is greater than or equal to zero, y/(x+y) is greater than or equal to 0.1, and z is sufficient to satisfy the requirement that Ga and A are substantially fully oxidized. Herein, Ga and A each are considered to be “substantially fully oxidized” if at least 80% (preferably at least 90%) of the respective element is fully oxidized, i.e., is in the highest oxidation state of the element. The highest oxidation state of Ga is 3+. The highest oxidation state of A depends on A. For instance, if A is an alkaline earth, then the state is 2+, and if A is Sc, Y, or a rare earth element, then the state is frequently, but not always, 3+.
The method of making the article comprises the steps of providing the GaAs-based semiconductor body, treating the body such that at least a portion of a major surface of the body is essentially atomically clean and essentially atomically ordered, forming, substantially without exposure of the semiconductor body to contamination, the oxide layer on the essentially atomically clean and ordered surface, and forming the metal contacts.
Significantly, the first forming step comprises forming the oxide layer such that the oxide layer has overall composition Ga
x
A
y
O
z
, where Ga substantially is in a 3+ ionization state, where A is one or more electropositive stabilizer element for stabilizing Ga in the 3+ ionization state, x is greater than or equal to zero, y/(x+y) is greater than or equal to 0.1, and z is sufficient to satisfy the requirement that Ga and A are substantially fully oxidized.
In an exemplary embodiment of the article, the oxide contains both Ga and A, and the stabilizer element A is Sc, Y or a rare earth (atomic number 57-71) element. In another exemplary embodiment the oxide layer is an essentially Ga-free oxide of a stabilizer element.
In an exemplary embodiment of the method the oxide layer is formed by simultaneous deposition from two (or possibly more) deposition sources, with one of the sources containing Ga
2
O
3
(typically in powder form), and the other containing an oxide of a stabilizer element (e.g., Gd
2
O
3
), typically also in powder from. In another exemplary embodiment the oxide layer is formed by deposition from a single deposition source containing an oxide of a stabilizer element, e.g., Gd
2
O
3
.
We have now made the surprising discovery that Gd
2
O
3
can be grown epitaxially, in single crystal, single domain form, on a GaAs-based semiconductor substrate. The single crystal oxide layer has low leakage current even for very small layer thickness, exemplarily less than 5 nm, and is advantageously used as gate oxide layer. By “GaAs-based semiconductor” we mean GaAs, ternary III/V alloys such as InGaAs, and quaternary Ga and As-containing III/V alloys such as AlInGaAs. Furthermore, we have found that Gd
2
O
3
can be grown in single crystal, single domain form on GaN and GaN-based semiconductors.
The above-described discovery makes possible the fabrication of MOS structures of increased capacitance per unit area. The increased capacitance is primarily due to the ability to use a thinner oxide layer than was previously possible.
We currently believe that the invention is not limited to the use of Gd
2
O
3

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